Verilog Quiz



Verilog Quiz # 3

The first Verilog quiz covering first 20 chapters of the Tutorial.


Q1. If A=1b1,B=2b01,C=2b00 y={4{A},2{B},C} equals

A . 10b1111010100
B . 9b111101010
C . 8b11110100
D. None

Q2. Case x treats

A . x as dont care
B . z
C . as dont care
D. Both x and z as dont care

Q3. If two signals of strong1 and weak0 contend which prevails

A . tri
B . triand
C . trior
D. trireg

Q4. Which net has storage strength

A . edge sensitive bit
B . level sensitive
C . both
D. none

Q5. wait statement is

A . edge sensitive bit
B . level sensitive
C . both
D. none

Q6. In continuous assignment LHS can be

A . Scalar net
B . Vector net
C . Concatenation of both
D. All of above

Q7. <= is used in

A . Blocking
B . Non Blocking
C . Both
D. None

Q8. Asynchronous reset is

A . Clock dependent
B . Clock independent
C . Either
D. None

Q9. 29. What could be the expression for below figure where in1 and in2 are input reg variables and out is output variable of wire type


A . assign out = in1&in2
B . assign #10 out = in1&in2
C . assign #30 out = in1&in2
D. assign #40 out = in1&in2

Q10. What would be simulation time in below code when rval=10

`timescale 1 ns / 1 ps
module timescale_check2;
reg[31:0] rval;
initial begin
rval = 20;
#10.566601 rval = 10;
end
initial begin
$monitor("TimeScale 1ns/1ps : Time=%0t,  rval = %d
",$realtime,rval);
#100 ;
end
endmodule


A . 0
B . 10567
C . 10566
D. 1056


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