Verilog Quiz



Verilog Quiz # 1

The first Verilog quiz covering first 20 chapters of the Tutorial.


Q1. Operator which precedes the operand

A . Unary
B . Binary
C . Ternary
D. None

Q2. Which is legal negative number

A . 4'd-3
B . 6'-d3
C . -6d'3
D. None

Q3. What is the default value for reg data type

A . 0
B . 1
C . z
D. x

Q4. What is system task to suspend simulation

A . $finish
B . $minitor
C . $display
D. $stop

Q5. Turn off delay means, gate output transition to

A . 1
B . 0
C . z
D. x

Q6. Parameter value can be overridden at module instance by

A . Specparam
B . Defparam
C . Parameter
D. None

Q7. In continuous assignment left hand side must be

A . Net
B . Reg
C . Scalar or Vector Net
D. Scalar or Vector reg

Q8. If in1 = 4b101x and in2 = 4b0101 then in1 + in2 equals

A . 0111
B . 0110
C . x
D. None

Q9. -10 % 3 evaluates to

A . -1
B . 1
C . 0
D. x

Q10. What are the possible values of == operator

A . 0,1
B . 0,x
C . 1,x
D. 0,1,x


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