### Verilog Hex to Seven Segment Display

We will be moving on to write slightly more complex example, this time a hex to seven segment encoder. Basically LED number is displayed with 7 segments.

The hexadecimal to 7 segment encoder has 4 bit input and 7 output. Depending upon the input number, some of the 7 segments are displayed. The seven segments are represented as a,b,c,d,e,f,g. A high on one of these segements make it display. For example to write 1 we need to display segments b and C.

The 7 segment display also has a decimal point dp.

The figure below explains this Let write this example making use of the verilog case statement
 `// www.referencedesigner.com // Verilog Tutorial// Hex to 7 Segment Example module hexto7segment( input [3:0]x, output reg [6:0]z );always @*case (x)4'b0000 : //Hexadecimal 0z = 7'b1111110;4'b0001 : //Hexadecimal 1z = 7'b0110000 ;4'b0010 : // Hexadecimal 2z = 7'b1101101 ; 4'b0011 : // Hexadecimal 3z = 7'b1111001 ;4'b0100 : // Hexadecimal 4z = 7'b0110011 ;4'b0101 : // Hexadecimal 5z = 7'b1011011 ; 4'b0110 : // Hexadecimal 6z = 7'b1011111 ;4'b0111 : // Hexadecimal 7z = 7'b1110000;4'b1000 : //Hexadecimal 8z = 7'b1111111;4'b1001 : //Hexadecimal 9z = 7'b1111011 ;4'b1010 : // Hexadecimal Az = 7'b1110111 ; 4'b1011 : // Hexadecimal Bz = 7'b0011111;4'b1100 : // Hexadecimal Cz = 7'b1001110 ;4'b1101 : // Hexadecimal Dz = 7'b0111101 ;4'b1110 : // Hexadecimal Ez = 7'b1001111 ;4'b1111 : // Hexadecimal Fz = 7'b1000111 ;endcase endmodule`

Note that we had to assign out as a register in

``` reg out; ```

In our case, it was not required because we had only one statement. We now suggest that you write a test bench for this code and verify that it works. If you have sifficulty, you can check it with following test bench

 ``timescale 1ns / 1psmodule stimulus; // Inputs reg [3:0] x; // Outputs wire [6:0] z; // Instantiate the Unit Under Test (UUT) hexto7segment uut ( .x(x), .z(z) );  initial begin // Initialize Inputs x = 0;  #20 x = 1; #20 x = 2; #20 x = 3; #20 x = 4; #20 x = 5; #20 x = 6; #20 x = 7; #20 x = 8; #20 x = 9; #20 x = 10; #20 x = 11; #20 x = 12; #20 x = 13; #20 x = 14; #20 x = 15; #40; end   initial begin \$monitor("x=%h,z=%7b",x,z); end endmodule`

``` Exercise 1. Change the above hex to BCD verilog code so that it take negative logic. A segment is on when it gets 0. A segment is off when it gets logic 1. <!-- google_ad_client = "ca-pub-9434406840590306"; /* referencedesigner-728-90 */ google_ad_slot = "9117919774"; google_ad_width = 728; google_ad_height = 90; //-->                 ```
```   ```
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