Verilog Quiz



Verilog Quiz # 9

Ninth Quiz


Q1. For tri0 what is the value when nothing is driving

A . 1
B . 0
C . x
D. z

Q2. For time check violation is reported if

A . Tdata_event Ė Treference_event) B . (Tdata_event Ė Treference_event) >limit
C . (Tdata_event Ė Treference_event) =limit
D. (Treference_event-Tdata_event) < limit

Q3. Which is object oriented programming

A . VHDL
B . Verilog
C . System Verilog
D. none

Q4. wand differs from wor in the way

A . wand forced to one if any driver to it is zero while wor forced to zero if any driver to it is zero
B . wand forced to zero if any driver to it is zero while wor forced to one if any driver to it is one
C . wand forced to zero if any driver to it is one while wor forced to one if any driver to it is zero
D. wand forced to one if any driver to it is one while wor forced to zero if any driver to it is zero

Q5. If there is mismatch in connecting wire such as
Y1[7:0] = Y2[15:0]


A . The end result is Y1[7:0]=Y2[15:0]
B . The end result is Y1[15:0]=Y2[7:0
C . The end result is Y1[7:0]=Y2[7:0]
D. Canít determine

Q6. What can be Verilog statement for 6 bit register constant C3 with decimal value of 30

A . Parameter C3=6íd30
B . C3=6íd30
C . Parameter C3=30
D. C3=30

Q7. What can be the Verilog code that declares an 6-bit register, R_H36, and initially assigns it the hexadecimal value 36

A . reg[5:0] R_H36;initial R_H36=6íh36;
B . reg [5:0] R_H36;R_H36=6íh36;
C . A,B
D. None

Q8. What could be timescale directive so that d1 and d2 corresponds to 0.3 and 0.7 respectively and simulator time step is 1ps

A . `timescale 1ps/ps
B . `timescale 100ps/ps
C . `timescale 100ns/ps
D. `timescale 1ps/@ps

Q9. Choose the right answer

A . UDPís are faster to simulate and require less memory than Verilog modules
B . UDPís are faster to simulate and require more memory than Verilog modules
C . UDPís are slower to simulate and require less memory than Verilog modules
D. UDPís are slower to simulate and require more memory than Verilog modules

Q10. Give a Verilog statement that instantiates the below RTL_circuit, with the instance name RT1, so that x has a delay of 7 time units and y has a delay of 5 time units
module RTL_circuit(x, y, a, b, c, d);
parameter x_delay = 3, y_delay = 7;
input a, b, c, d;
output x, y;
assign #y_delay y = (a | b) & (c | ~d);
assign #x_delay x = a ^~ b;
endmodule


A . RTL_circuit #(7,5) RT1(y,x,a,b,c,d);
B . RTL_circuit #(5,7) RT1(y,x,a,b,c,d);
C . #(5,7) RTL_circuit RT1(y,x,a,b,c,d);
D. RTL_circuit #(7,5) RT1(x,y,a,b,c,d);


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