## Verilog Language Continued

 Vector Data

In the single bit comparator example we had only two sets of 1 bit input. What if we need to design a comparator that has two sets of 2 bit input ? Verilog provides the concept of Vectors. Vectors are used to represent multi-bit busses.

A vector to represent a multi bit bus is declared as follows

reg [7:0] eightbitbus; // 8-bit reg vector with MSB=7 LSB=0

The reg [7:0] means you start with 0 at the rightmost bit to begin the vector, then move to the left. We could also declare the vector as

reg [0:7] eightbitbus; // 8-bit reg vector with MSB=0 LSB=7

In which case the LSB will be represented by leftmost bit.

Let us rewrite our comparator example, so that it now use two bit bus in place of one bit.

 ``timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: referencedesigner.com //////////////////////////////////////////////////////////////////////////////////module comparator2bit( input [1:0] x, input [1:0] y, output z ); assign z = (x[0] & y[0] & x[1] & y[1]) | (~x[0] & ~y[0] & x[1] & y[1]) | (~x[0] & ~y[0] & ~x[1] & ~y[1])| (x[0] & y[0] & ~x[1] & ~y[1]);endmodule  `

 ``timescale 1ns / 1psmodule stimulus; // Inputs reg[1:0] x; reg[1:0] y; // Outputs wire z; // Instantiate the Unit Under Test (UUT) comparator2bit uut ( .x(x), .y(y), .z(z) );  initial begin \$dumpfile("test.vcd"); \$dumpvars(0,stimulus); // Initialize Inputs x = 0; y = 0; #20 x = 1; #20 y = 1; #20 y = 3; #20 x = 3; #20 y = 1; #20 y = 0;   #40 ;  end   initial begin \$monitor("t=%3d x=%2b,y=%2b,z=%d \n",\$time,x,y,z, ); end endmodule `

This example produces the following result in console
``` ```
t=  0 x=00,y=00,z=1

t= 20 x=01,y=00,z=0

t= 40 x=01,y=01,z=1

t= 60 x=01,y=11,z=0

t= 80 x=11,y=11,z=1

t=100 x=11,y=01,z=0

t=120 x=11,y=00,z=0
``````
` ` Note that the assignment x =3 means 11 in binary.

The verification is only partial and we would let the reader write code that will verify it exhaustively. You may also write a self verifying code by checking the output z against expected value.

Thanks Rodney Schaerer for mentioning error in the stimulus code.