## Verilog if in Combinatorial circuit

 if statement

The ` if ` statetement in verilog is very similar to the if statements in other programming languages. We will now write a combinatorial verilog example that make use of if statement. Let us try to design a priority encoder. Our priority encoder has 4 bit inputs - call them x, x,x. x. The x bit has the highest priorty. The x bit has lowest priority. At any point of time more that one inputs may be high. Our circuit will check which is the bit with highest priority. And then it gives the binary code of the position of the highest output. If none of the inputs is high, then its out put is 0. The table below shows the behavior of the priority encoder.

Table: A priority encoder with 4 Inputs

 x x x x Output z 1 - - - 100 0 1 - - 011 0 0 1 - 010 0 0 0 1 001 0 0 0 0 1

The - in the table means - it does not matter if the input is 0 or 1. When the x input is 1, it has highest priority and irrespective of the values of other bits, we will give the output that corresponds to the binary digit corresponding to 4 in x or 100. Similarly, if the x is zero and the priority of the next bit x is high, then irrespective of the values of x and x, we give output corresponding to 3 of x - or 011. We follow the same logic as per the table above.

Let us now write the actual verilog code that implement the priority encoder

 `module priory_encoder(input wire [4:1] x,output reg [2:0] pcode ); always @(x, x,x, x) if (x == 1'b1) pcode = 3'b100;else if (x == 1'b1) pcode = 3'b011;else if (x == 1'b1) pcode = 3'b010; else if (x == 1'b1) pcode = 3'b001; else pcode = 3'b000; endmodule `

Note that the always statement ``` always @(x, x,x, x) ``` Could be written as ``` always @ * ``` We now suggest that you write a test bench for this code and verify that it works. If you have sifficulty, you can check it with following test bench

 ` `timescale 1ns / 1psmodule stimulus; reg [4:1] x; wire [2:0] pcode; // Instantiate the Unit Under Test (UUT) priory_encoder uut ( .x(x), .pcode(pcode) );  initial begin // Initialize Inputsx = 4'b0000;   #20 x = 4'b0001; #20 x = 4'b0010; #20 x = 4'b0011; #20 x = 4'b0100; #20 x = 4'b0101; #20 x = 4'b0110; #20 x = 4'b0111; #20 x = 4'b1000; #20 x = 4'b1001; #20 x = 4'b1010; #20 x = 4'b1011; #20 x = 4'b1100; #20 x = 4'b1101; #20 x = 4'b1110; #20 x = 4'b1111; #40 ;  end   initial begin \$monitor("t=%3d x=%4b,pcode=%3b",\$time,x,pcode ); end endmodule  `

Notice the use of the if statement
``` if (x == 1'b1) pcode = 3'b100; else if (x == 1'b1) pcode = 3'b011; ```

The general syntax of an if statement is as follows ``` if [boolean-expr] begin [procedural statement] ; [procedural statement] ; end else begin [procedural statement] ; [procedural statement]; end ``` The `boolean-expr` is evaluated and if it is true, the list of the procedural statements between `begin` and `end` is executed. If the `boolean-expr` is false the procedural statements in the `else ` block is executed. The `begin` and `end` can be omitted if there is only one procedural statement as in the case of our example. The `else` statement can become `else ` statement if we wish to check second condition.

## A Binary Decoder Example

We will now present another example that will make use of `if ` statement. A Binary decoder is a circuit that has n inputs and 2n outputs. It asserts one and only one 2n outputs depending upon the input.

Let us say our binary decoder has 2 inputs x and x and 4 outputs y, y, y, y.

We are also making the decoder circuit a bit more complicated by requiring an enable signal. If the enable is 0 ( means it is disabled), the output will be 4'b0000.

The table below shows the function of the Binary decoder.

Table: A 2 to 4 binary Decoder with Enable Signal

 Enable x x Output y[3:0] 0 - - 0000 1 0 0 0001 1 0 1 0010 1 1 0 0100 1 1 1 1000

Can you now try to implement the above on your own without looking at the code presented below.
 `// Referencedesigner.com // Binary Decoder Example - Usage of if// Verilog Tutorial  module binary_encoder(input wire [1:0] x,input wire enable,output reg [3:0] y ); always @(enable, x,x) if (enable == 1'b0) y=4'b0000;else if (x == 2'b00) y = 4'b0001;else if (x == 2'b01) y = 4'b0010;else if (x == 2'b10) y = 4'b0100;else if (x == 2'b11) y = 4'b1000; endmodule `

Note that the if statement

``` if (enable == 1'b0) ```

Could also be written as

``` if (~enable) ```

We now suggest that you write a test bench for this code and verify that it works. If you have sifficulty, you can check it with following test bench

 ` `timescale 1ns / 1psmodule stimulus; reg [1:0] x; reg enable; wire [3:0] y; // Instantiate the Unit Under Test (UUT) binary_encoder uut ( .x(x), .enable(enable), .y(y) );  initial begin // Initialize Inputsx = 4'b0000; enable = 0;   #20 enable = 1; #20 x = 2'b01; #20 x = 2'b10; #20 x = 2'b11; #40 ;  end   initial begin \$monitor("t=%3d enable=%1b,x=%2b, y=%4b",\$time,enable,x,y ); end endmodule  `

 Exercise

1. Run the above two examples and verify that the output is as expected.