Minimum Impedance Requirement of an IC with IO gates switching.
7.4 Minimum Impedance Requirement of an IC with IO gates switchingWe have already seen, providing the low ac impedance between the power and ground rail at all frequency is key to achieving noiseless power supply. How low should be the required ac impedance? It will depend upon how fast the components on the PCB draw the current. Here are the steps required to calculate the required low impedance.
1. Find the maximum change of current DI. We can assume a worst case when all gates switch simultaneously and create a worst DI.
2. If an IC has N gates with load capacitance of C pf each and the swing is T seconds then the rate of current can be calculated as
DI = N*C *V / T [7 6]
where V is the logic high voltage level of the circuit.
3. Find the maximum value of the DV that a logic gate can tolerate. The maximum value of the impedance ( due to power supply wiring) that can be tolerated is given by .
Xmax = DV/DI
Example 7.4 - Assume that a PCB has CMOS gates and that in worst case it draws a current of 2 A. The voltage level is 3.3V. The maximum allowed voltage change is 5%. Find the maximum value of the impedance required between the power and ground pins required, so that the noise voltage does not exceed 5% of 3.3V.
Solution -
The noise margin of the circuit is given by dV = 3.3V * 5 /100 = 0.165V
The maximum impedance of the load that need to be tolerated
X = dV/dI = 0.165V / 2A = 0.0825 Ohms.
The result says that if the impedance between the power and the ground is 0.0825 Ohms or less, the noise ripple will get shorted. We create the low impedance path using capacitors. In the later section of this chapter we will see how to achieve low impedance across all frequency ranges using capacitors.
Example 7.5 - A CMOS circuit board has an IC having 100 gates. Assume that each gate has a load capacitance of 5 pf. The switching time is 5 ns. Find the value of the bypass capacitor. Assume high logic level of 3.3 V and a voltage tolerance of 0.1V. Find the maximum impedance between the power and ground pins achieved by the use of capacitors which will tolerate this voltage ripple of 0.1V.
Solution
According to the current equation
DI = N*C *V / T
= 100 * (5 pf)*3.3 / ( 5 ns)
= 0.33 A.
The maximum impedance that can be tolerated is given by
X = dV/dI = 0.10V / 0.33A = 0.30 Ohms.
Example 7.6 - A CMOS circuit board has an 4 ICs. The number of gates and characteristics are as follows
IC1 : 40 gates, load capacitance of 5 pf. switching time is 5 ns.
IC2 : 100 gates, load capacitance of 8 pf. switching time is 2 ns.
IC3 : 50 gates, load capacitance of 10 pf. switching time is 4 ns.
Find the maximum impedance that can be tolerated, assuming , it can tolerate 0.1V of voltage ripple.
Solution
Assume high logic level of 3.3 V and a voltage tolerance of 0.1V. Find the maximum impedance between the power and ground pins achieved by the use of capacitors which will tolerate this voltage ripple of 0.1V.
According to the current equation
DI = N*C *V / T
The current by the first IC,
DI1 = N*C *V / T
= 40 * (5 pf ) * 3.3V / (5 ns)
= 0.132 A
The current by the second IC,
DI2 = N*C *V / T
= 100 * (8 pf ) * 3.3V / (2 ns)
= 1.32 A
The current by the third IC,
DI3 = N*C *V / T
= 50 * (10 pf ) * 3.3V / (4 ns)
= 0.416 A
Assuming worst case scenario when all ICs switch together,
Total current DI = DI1 + DI2 + DI 3
= 0.132 A + 1.32 A + 0.416A
= 1.868 A
The maximum impedance that can be tolerated is given by
X = dV/dI = 0.10V / 1.868A = 0.053 Ohms.
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