HyperTransport Differential Bus

HyperTransport bus is scalable differential bus used to connect processor to processor, or processor to bridges. It was steered by AMD (Advanced Micro Devices). The HyperTransport  signals constitute a single unidirectional connection between two nodes. A full link requires a connection in each direction. A group of HyperTransport signal consist of one CTL signal to distinguish between control or data signal. It has scalable number of CAD (Command, Address, DATA) signals. The number of CAD signal can be 2, 4, 8, 16 or 32. If there are 2, 4 or 8 CAD signals then the HyperTransport bus has one CLK signal. If it has 16 CAD signals, then it has 2 CLK signals. If there are 32 CAD signals, it has 4 CLK signals.

 

The HyperTransport link uses on-die differential termination. It has scalable data transfer rates of 400 million transfers per second (MT/s), 600 MT/s, 800 MT/s, 1.0 GT/s, 1.2 GT/s, and 1.6 GT/s. Using scalable frequency and data width, HyperTransport bus has ability to achieve scalable bandwidth.

 

HyperTransport Consortium has released details of the HyperTransport 3.1 specification, which increases the clock speed  to 3.2 GHz (6.4 GTransfers/s).   With a 32-bit wide, the total aggregate bandwidth in the two directions is  a massive 51.6 GB/s (25.8 GB/s in each direction).

 

We will take a look at some of the electrical specification of HyperTransport. HyperTransport recommends a RON for pull up as well as pull down resistance between 45 to 55 Ohms. RON  is the driver output impedance under DC conditions. RTT, the value of the differential input impedance of the receiver under DC conditions, has been specified to be between 90 Ohms to 110 Ohms.

 

HyperTransport has a both end termination to minimize the reflection. The on die termination simplifies the PCB design in addition to reducing the stub that would have been created when placing the RON terminations away from the driver. A tighter control of the driver RON resistance, as well as the tigher control of receiver RTT resistance ensures minimal reflection.

 

The effective differential source impedance of driver lies between 90 Ohms to 110 Ohms. Assuming that the signal is coupled into a perfect 100 Ohm transmission line, the worst case reflection is given by

 

            Γ = (90-100)/(90+100)  = -0.05

 

The worst case reflection at the receiver end is given by ( assuming the minimum RTT to be 90 Ohm)

 

Γ = (90-100)/(90+100)  = -0.05

 

Multiplying the two reflection coefficients, we arrive at the conclusion that the amplitude of the reflected signal will be less than 0.25% guaranteed by design ( assuming of course the perfect transmission line impedance of 100 Ohm). It is not unreasonable to assume that the transmission line differential impedance can be controlled to remain  between 90 to110 Ohms. The worst case reflection will be when the differential source impedance and differential receiver termination impedance are both 90 Ohms and the transmission line impedance is 110 Ohm. The reflection coefficient in such a case is given by,

Γ =  Γ₁ Γ₂

Where, Γ₁ and Γ₂ are reflection coefficients at transmitter and receiver and are given by

Γ₁ = Γ₂ =  (90-110)/(90+110)  = -0.1

 

This gives,

Γ =  0.01

This ensures that the maximum reflection is of the order of 1%.

 

HyperTransport achieves a better worst case reflection performance than the LVDS by laying down tighter control on the driver side on die termination. HyperTransport specifies a maximum load capacitance of 2pf on each of the receiver pins. The capacitive loads will cause some negative reflection that can be potentially partially balanced by the inductive package traces.

 

HyperTransport is a robust technology. Advanced Micro Devices has successfully used it for multiprocessor interconnect for their Opteron series of processor to achieve massive bandwidth.

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