EMI - Question Answer

Signal Integrity Tips As a PCB designer you do not have time to read the detailed theories of signal integrity. The least you can do is to keep in mind certain basic design rules that will ensure “reasonably” good design from signal integrity perspective.
Tips for Integrity of Point to Point Signal

1. For all high speed signals use controlled impedance traces.
2. Design a correct layer stack up to meet power and impedance requirement
3. Calculate the required trace width for the required impedance using field solver. You can use a dedicated 2D field solver or the in built filed solver in the PCB design software.
4. If you use series, use a value to match the impedance. The series impedance of driver plus the value of series resistance should match the characteristic impedance of trace.
5. Place series terminating resistor as close to the driver IC as possible.
6. Keep the high speed traces as small as possible.
7. Use smaller vias in the path of high speed signals. Vias create capacitive discontinuity. Increasing the antipad diameter reduces the capacitance of the via.
8. Match the timing relation between clock and data signals using length and time delay calculations. Account for the fact that signals travel faster in microstrip than in stripline.
9. Match the lengths of the two signals of the differential pair. Use automatic rules checking in the PCB software and also manually inspect the critical differential signals.
10. Keep the routing of the differential signals symmetrical. Keep the number and placement of the vias symmetrical.
11. If the differential signal needs to be spaced apart, adjust the width of the trace to maintain the differential impedance.
12. If signal is sensitive to path loss, keep the trace width at least 5 mils, the larger the better. Minimize length of the trace.
13. If signal is sensitive to the path loss, minimize capacitive discontinuity, use minimum number of vias in the path of trace.
14. If the signal is sensitive to path loss, minimize dielectric loss by using material with low loss.
15. If there is an impedance discontinuity and if the electrical length of the discontinuity is less than 1/6th of the rise time of the signal try to compensate it. A capacitive discontinuity should be matched with an inductive discontinuity. An inductive discontinuity should be matched with a capacitive discontinuity.
16. Minimize power plane discontinuity, especially if a high speed signal use it as a reference plane for return current.
17. If multiple powers share a power plane, and if the power plane is used as a reference plane for return signal of high speed traces use stitching capacitors to “stitch” the boundaries of the power plane islands.
18. Make a check list for all signal integrity rules and have someone check the design and sign off the check list.
19. Use smaller resistor size (prefer 0402 over 0603 or 0805) in the path of high speed signal to minimize discontinuity due parasitics of resistor.
20. Calculate and predict extent of discontinuity at connectors in the path of high speed signals. Connectors usually add inductive discontinuity. It can be compensated by adding pads at the two ends of the connector. This works very well if the electrical length is 1/6th or less compared to signal rise time.
21. If the signal uses a terminating resistor, place them as close to the IC as possible.


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