Power Planes Ch 6

6.10 Tom and Bob

Tom – Hey Bob, I just got started with the design for a 4 Layer stack up. I designed with Layer2 with ground and Layer3 with VCC. The top and bottom layers are for routing, including high speed signaling. Now this PCB is standard 0.063”. I was told that the separation between the power and ground planes should be as small as possible. But I need to keep my top and bottom layer controlled impedance 5 mils to get the required impedance. With that, the separation between power and ground layers will be too high – about 50 mils. Is it not too high. What do I do ?

Bob – An excellent question Tom. You have advanced information about controlled impedance and let me congratulate you about this. The power plane capacitance is almost non existence which, as you will see later, is required for very high frequency filtering. You have following options.

1. If your mechanics allows, reduce the total thickness of the board to, say, 0.033” in place of 0.063”. This will make the board thinner and you will have to see if this thickness is acceptable. Electrically, this will reduce the power and ground separation, and provide more power and ground plane capacitance.

2. Fill up the unused areas of the top and bottom layers with ground and power copper. If layer 2 is a ground layer, fill up top l layer with power. If layer 3 is a power layer, fill up layer 4 with ground layer. This will provide some additional power to ground plane capacitance.

3. If it is not too expensive consider upgrading to a 6 layer stackup. You should consider this option if your board is sensitive to the high frequency noise in the power plane.

Tom – I designed a six layer stack up with

Signal 1
Ground
Signal 2
Signal 3
Power
Signal 4

In the stuck up I do not get significant power and ground plane coupling. How can minimize the effect of the lower power plane decoupling

Bob - You should fill up unused areas on the Signal 1, Signal 2, Signal 3 and Signal 4 layers. That should provide some additional power ground capacitance. In this stackup you should also be careful about providing stitching capacitors in the different power islands in the Power plane.

Tom – I am designing a new board that is based upon a reference design that I received from the chip designers. The original design has 14 layers. Since we want to take the design to production, we want to reduce the number of layers. What are the things that I should be concerned when reducing the number of layers

Bob – Most of the basic signal integrity requirements are fulfilled with 8 Layer stack up. There is really no big advantage of the increasing the number of layers beyond 8 layers. An 8 layer stack up, can provide good power ground coupling, tight signal to power ground coupling. Increasing the layers exceeding 8 is meaningful only if you are out of space in routing signals. This will depend upon the density of the BGA IC that you are using.

I will let you reduce the stack up to 8 layers. Don’t reduce it below 8 layers. Reducing below 8 layers will mean that you are sacrificing one or more signal integrity concerns.

Practically you should do it step by step. If your original design has 6 power and ground layers and 8 signal layers, then first remove a pair of ground and layer. Move the power islands of the removed power plane into the existing power planes. That reduces the number of layers to 12. Now find which two layers have least density of signals. Removes these two layers and make sure you can still route the un routed signals in the existing layers. This reduces the number of layers to 10. Probably you would like to stop here. But you can keep moving and remove two more signal layers. Do not reduce the total number of power planes (ground + power) below 4.


Previous - Symmetry and Board Warping                                Next - Chapter 7 - Power Supply DC perspective