Length Matching examples - PCI Bus Clocks
CHAPTER 22.7 Length Matching examples - PCI Bus Clocks
Clocks to all PCI devices in a system are typically generated from a clock multiplier like Texas Instruments’ CDCV304PW. A typical PCI bus clock implementation has a clock oscillator going to the input of a clock multiplier. The clock multiplier typically gives out 4 outputs. These four outputs go to the 4 PCI devices. The length of these clock nets are required to be matched.
In motherboard designs there is an additional clock delay on the PCI add on cards. In order to make the overall lengths of the clock same, a rule has been made, which states that the length of the clock will be fixed to 2.5” on PCI add on cards. The motherboard design requires that the length of the clock going to the PCI add on slots will be less by 2.5”. With the PCI add on cards inserted, the clock lengths match.
In a design where there is no add on slot, the length of the clocks should match. A typical embedded system has all PCI devices on the board itself. In such case, the lengths of clock nets should match. There is no matching requirement on the length of the Address / Data signals with respect to clock signal, though, there is a limitation on the maximum length of the Address / Data signal length depending upon the PCI Bus speed.
The length matching of clock signals in PCI bus is not very critical. It is however, often, not too difficult to match it within 100 mils. If the things gets difficult it may be relaxed to 250 mils.
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