Implementation of Clocking Schemes
CHAPTER 22.6 Implementation
Most modern commercial PCB design softwares have capability to set length matching or flight time matching ability inside the software. The software will flag a DRC error if the matching rule is violated. The software requires you to create a group of signal or create a matching pair and mention the allowed length or time mismatch. If the PCB design software provides these features we must avail of the opportunity. The advantage of this method is that we need to work only one time to define the constraints. If there is a change in the routing, we just need to run the DRC (Design Rule Check).
If the feature is not provided in the PCB design software, there is usually a report generation facility in the PCB design software that can be utilized. The report may be verbose. It may require string processing using some scripting software. The scripting software should tabulate the nets and automatically find the violations.
Many times a signal integrity engineer uses words like “as small as possible” to describe the difference in length of matching group signal. This helps neither the automation software nor the PCB design professional to successfully implement the constraint. In such a case, the PCB design engineer and signal integrity engineer should meet and decide a reasonable figure for all statements like – “place the series termination resistance R1 as close to IC U1 as possible”. The PCB design engineer and the signal integrity engineer can agree upon a reasonable tighter limit initially. If the routing is difficult with the tighter limit for some nets, they can meet again to relax the limits and renegotiate the constraints. The signal integrity engineer will recheck that the relaxed constraints do not break the design.
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