Verilog Quiz



Verilog Quiz # 7

Seventh Quiz

Q1. Which of the following is true about always statement

A . There may be exactly one always block in a design.
B . There may be exactly one always block in a module
C . Execution of an always block occurs exactly once per simulation run
D. An always block may be used to generate a periodic signal

Q2. In most synthesis tools, what will happen when a signal that is needed in a sensitivity list is not included?

A . An error will be generated and the code cannot be synthesized.
B . A warning message will be generated and the code will be synthesized but the resulting netlist will not provide the desired results
C . The synthesis tool will ignore the sensitivity list since all objects that are read as part of a procedural assignment statement are considered to be sensitive
D. There will be no effect on the design and pre-synthesis simulation will be consistent with post-synthesis simulation.

Q3. Which of the following is used for Verilog-based synthesis tools?

A . Intra-statement delay statements can be synthesized, but interstatement delays cannot
B . Inter-statement delay statements can be synthesized, but intrastatement delays cannot
C . Initial values on wires are almost always ignored.
D. Synthesized results are identical for "if" and " case " statementst

Q4. Consider the following choices below. To comment Verilog Code, one may use:

I A "Double-slash" // for a single-line comment.
II Multiple "Double-slashes" (one per line) for a multiple-line comment.
III A "Block-comment" /* */ for a single-line comment.
IV A "Block-comment" /* */ for a multiple-line comment.

A . I and II
B . I and IV
C . II and III
D . I, II, and IV
E . I, II, III and IV

Q5. Analyse the circuit given below with logic delays dly1,dly2,dly3



How can we fix hold and setup time violation in pinB

A . Change dly3
B . Change dly2
C . Change dly2 and dly3
D. Change dly1,dly2,dly3

Q6. What is the value of a in given Verilog code

always @(clk) begin
   a  = 0;
   a <= 1;
   (a);
end


A . a =1
B . a=1
C . Both of above
D. A=0 in this simulation and a=1 would be in next simulation

Q7. Analyse the code segment given below and choose right answer

 module top;
-------
---------
assign a=a&b|c;
-------
-------
initial begin
#50 force out = a&b&c;
#50 release out;
end
-----------
------
endmodule

A . Expression a&b&c is assigned to net from time 50 to 100
1. a&b&c overrides assignment of a&b
1. a&b&c overrides assignment of a&b
D. A, C

Q8. keywords "assign" "deassign" are

A . continuous assignment
B . procedural continuous assignment
C . blocking assignment
D. nonblocking assignment

Q9. What is missing in top module of below code segment 

module my_verilog;
parameter p1 = 5;
initial
 ("displaying my_vrilog = %d",p1);
endmodule
module top;
defparam q1.p1=6,q2.p1=4;

endmodule


A . Initial statement
B . One module instance of my_verilog
C . Two module instance of my_verilog
D.

Q10. The below figure is an example of



A . Pin to Pin delay
B . Distributed delay
C . Lumped
D. None


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