Verilog Quiz



Verilog Quiz # 6

Sixth Quiz

Q1. The left hand side of procedural continuous assignment can be

A . Register or concatenation of registers
B . Net or concatenation of nets
C . Can be both registers or nets
D. Array of registers

Q2. Which of the following about resistive switches is correct

A . Low source to drain impedance
B . High source to drain impedance
C . Retain signal strength
D. None

Q3. Which of the following about UDP’s are correct

A . UDP can be defined inside modules
B . UDP can be instantiated inside module
C . UDP supports inout ports
D. UDP can take both scalar and vector input

Q4. For the diagram given below choose the correct answer



A . Propagate z if cntrl is asserted
B . Propagate z if cntrl is deasserted
C . Propagate 1 if cntrl is asserted
D. None

Q5. For the segment given below choose the correct answer

bufif0 #(5,6,7) c1(out,in,cntrl)

A . 5=rise 6=turnoff 7=fall
B . 5=fall 6=rise 7=turnoff
C . 5=rise 6=fall 7=turnoff
D. 5=turnoff 6=rise 7=fall

Q6. STA(static timing analysis) is a method

A . Of computing expected timing without using simulation
B . Of computing expected timing using simulation
C. None

Q7. Which of the following is equivalent to logic level 1

A . 1
B . 1'b1
C . 1`b1
D . All of above
E. A,B

Q8. If X is a ten digit number which of the following will left extend X[9] three times

A . {(X[9], X[9], X[9]), X}
B . (X[9], X[9], X[9], X)
C . {3(X[9]), X[9]}
D. {3{X[9]}, X[9]}

Q9. Which of the following pertains to parameters

A . The default size of a parameter in most synthesizers is the size of an integer, 32 bits
B . Parameters enable Verilog code to be compatible with VHDL
C . Parameters cannot accept a default value
D . All of above
E. None of the above

Q10. Which of the following is not true about operators ?

A . A logical "or" is performed by writing "C = A || B;"
B . ‘!’ performs logical negation while ‘~’ performs bitwise negation
C . The two types of "or" operators are "logical" and "bitwise."
D. The "shift right" (>>) operator inserts zeros on the left end of its argument


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