Verilog Quiz



Verilog Quiz # 5

The first Verilog quiz covering first 20 chapters of the Tutorial.

Q1. Arrays are not allowed for

A . integer
B . register
C . time
D. real

Q2. Which directive is used to include entire content of Verilog source Into another file

A . 'include
B . 'ifdef
C . 'ifndef
D. None

Q3. All ports by default are

A . reg
B . inout
C . wires
D. Should be defined

Q4. Inout ports must always be

A . reg
B . net
C . trireg
D. none

Q5. Which is used to introduce delays in circuit

A . Inverter
B . XOR gate
C . Buffer
D. Flip fops

Q6. Flip flop is

A . Monostable multivibrator
B . Astable multivibrator
C . Bistable multivibrator
D. None

Q7. For the diagram given below



A . Frequency of Y equals frequency of clk
B . Frequency of Y is double the frequency of clk
C . Frequency of Y is half the frequency of clk
D. Can’t determine

Q8. NMOS transistor passes

A . strong0
B . strong1
C . weak0
D. weak1

Q9. If a variable is not assigned in all possible execution of always statement then

A . A don’t care is inferred
B . Latch is inferred
C . Variable is set to 0
D. Synthesis process will fail

Q10. 50. Analyse below code segment to choose correct answer 
always @(irq)
begin
{in2,in1,in1} = 3'b0;
casez (irq)
3'b1?? : in2 = 1'b1;
3'b?1? : in1 = 1'b1;
3'b??1 : in0 = 1'b1;
end

A . This is non full case
B . This is full case
C . This is parallel case
D. Case which is not parallel


Try other quizzes

Quiz 1

Quiz 2

Quiz 3

Quiz 4

Quiz 5

Quiz 6

Quiz 7

Quiz 8

Quiz 9