module zero; reg a,b,c; //initial block with zero delay initial begin #0 a = 1; #0 b = 1; #0 c = 1; (" Zero delay control a= %b, b= %b, c=%b ",a,b,c); end //initial block without zero delay initial c = 0; initial begin a = 0; b = 0; ("Non-zero delay control a= %b, b= %b, c=%b ",a,b,c); end endmodule
reg clock; initial begin clock = 1'b0; foever #10 clock = ~clock; end