Verilog Quiz



Verilog Quiz # 2

The first Verilog quiz covering first 20 chapters of the Tutorial.

Q1. What is the time period of clock #10 clock = ~clock

A . 10
B . 20
C . 5
D. None

Q2. #40 $finish indicates

A . end of simulation time
B . end of simulation at 40 time units
C . suspend simulation at 40 time units
D. None

Q3. @posedge means

A . Transition from 0 to 1,x or z
B . Transition from x to 1
C . Transition from z to 1,x
D. All of Ablve

Q4. What is the width of time register

A . 16 bit
B . 32 bit
C . 64 bit
D. 1268 bit

Q5. %g or %G displays

A . Real numbers in decimal or scientific notation
B . Real numbers in decimal or scientific notation whichever shorter
C . Real numbers in scientific format
D. Real numbers in decimal format

Q6. Parameter value can be overridden at module instance by

A . `define
B . `include
C . `ifdef
D. `timescale

Q7. If x=4’b1100 then x<<2 is

A . 4’b1000
B . 4’b0000
C . 4’b0011
D. 4’b0110

Q8. If x=4’1100 then &x equals

A . 1'b0
B . 1'b1
C . 4'b1100
D. None

Q9. If A=4’b1010 and B=4’b1100 then A&B

A . 4'b0000
B . 4'b1000
C . 1'b1
D. 1'b0

Q10. If A=1’b1,B=2’b01,C=2’b00 then y= {A,B[0],C[1]} equals

A . 3'b110
B . 3'b100
C . 3'b101
D. 1'b0


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