Ring Counter

4 bit ring counter is a circuit that counts in the fashion shown below 

0001
0010
0100
1000
0001
..
..
and so on


At the time of reset the value of the counter is initialized to, say, 0001. It then becomes 0010 at the next clock cycle - and this keeps going on. Basically there is one bit that keeps shifting to left 1 bit at each clock cycle and then it rolls over when it reaches MSB. Here is the verilog implemmentation of ring counter. 


  1. // referencedesigner.com 
  2. // 4 bit ring counter example 
  3. module four_bit_ring_counter (
  4.       input clock,
  5.       input reset,
  6.   output [3:0] q
  7.     );
  8.  
  9.   reg[3:0] a;
  10.  
  11.     always @(posedge clock)
  12.       if (reset)
  13.         a = 4'b0001;
  14.  
  15.       else
  16.         begin
  17.         a <=  a<<1; // Notice the blocking assignment
  18.         a[0]<=a[3];
  19.         end
  20.  
  21.     assign q = a;
  22.  
  23.   endmodule


Some Explanation

At the time of reset we make the ring counter to start at 4'b0001; 

a = 4'b0001;


When it comes out of reset, we use two statements to update the ring counter at each cycle. 

a <= a<<1; // Notice the blocking assignment
a[0] <= a[3];


Notice that we have used non blocking assignment and not blocking assignment. You can think of it as follows. Just before the clock cycle, mentally calculate a<<1 in a temporary register. Also mentally assign a[0] the value of a[3], BEFORE the execution of the a<<1. Now at the rising edge of the clock the two assignmenta take place.

For example let us say current value of a is 0010. The the left shift assignment will shift it to 0100. The a[0] <= a[3] will not change anything.

Now when the value of the a is 1000, then we have to be careful. The left shift a<<1 assignment is tending to make a to 4'b0000. But remember, we have used non blocking assignment. So the next non blocking statement a[0] <= a[3] takes effect. This statememt, takes the value of a[3] which is 1'b1. Now mentally store is in your mind and at the next clock cycle assign it to a[0].

If, however, you use blocking assignment staatements like 

a = a<<1; 
a[0] = a[3]


Then counting from 4'b1000 to 4'b0000 may have an issue, and the simulator may result in rolling over to 4'b0000

Here is a test bench for the ring counter. 

  1. `timescale 1ns / 1ps
  2. module stimulus;
  3. 	// Inputs
  4. 	reg clock;
  5. 	reg reset;
  6. 	// Outputs
  7.   wire[3:0] q;
  8. 	// Instantiate the Unit Under Test (UUT)
  9. 	four_bit_ring_counter r1 (
  10.       .clock(clock), 
  11.       .reset(reset), 
  12.       .q(q)
  13. 	);
  14.  
  15.   always #10 clock = ~clock;
  16.  
  17. 	initial begin
  18. 		// Initialize Inputs
  19.     clock = 0;  
  20. 	reset = 0;
  21.  
  22. 	#5 reset = 1;
  23. 	#20 reset = 0; 
  24. 	#500 $finish;
  25.     end  
  26.  
  27. 		initial begin
  28.           $monitor($time, " clock=%1b,reset=%1b,q=%4b",clock,reset,q);
  29. 		 end
  30.  
  31. endmodule