Gate Level Modeling


Gate Level Modeling

Although the circuit behaviour in verilog is normally specified using assignment statements, in some cases modeling the circuit using primitive gates is done to make sure that the critical sections of circuit is most optimally laid out.

Verilog has built in primitives like gates, transmission gates, and switches to model gate level simulation. To see how the gate level simulation is done we will write the Verilog code that that we used for comparator circuit using primitive gates. 


  1. module gate(
  2.     input x,
  3.     input y,
  4.     output z
  5.     );
  6. 	wire x_, y_, p,q;
  7. 	not(x_, x);
  8. 	not(y_, y);
  9. 	and(p, x,y);
  10. 	and(q, x_,y_);
  11. 	or(z,p,q);
  12.  
  13. endmodule


This example does the same fuction as the previous example, but we have used primitive gates in this example


Explanation


The primitive

not (x_, x);

creates a not gate with x as input and x_ as output. All primitives has at least two parameters. The first parameter is output and other parameters are input. The statement

and(p, x,y);

creates an AND gate with two inputs and one output.

You can simulate the code with same stimulus that we did in the previous example, which is reproduced here. 

  1. initial begin
  2. 		// Initialize Inputs
  3. 		x = 0;
  4. 		y = 0;
  5.  
  6. 		// Wait 100 ns for global reset to finish
  7. 		#100;
  8. 		#50 x = 1;
  9. 		#60 y = 1;
  10. 		#70 y = 1;	
  11. 		#80 x = 0;			
  12. 	end


And it produces the same output 

x=0,y=0,z=1 
x=1,y=0,z=0 
x=1,y=1,z=1 
x=0,y=1,z=0

In the next page we will learn about User Defined Primitives ( UDP).