Verilog TUTORIAL with Icarus| Verificatiom


Now we have understood the concept we will compile the code and and run it in Icarus. Copy the following source codes in the directory C:\iverilog\bin.



comparator.v 

  1. module comparator(
  2.     input x,
  3.     input y,
  4.     output z
  5.     );
  6.  
  7. assign z = (~x & ~y) |(x & y);
  8.  
  9. endmodule


stimulus.v 

  1. // referencedesigner.com verilog tutorial
  2. // testbench for comparator module
  3. `timescale 1ns / 1ps
  4. module stimulus;
  5. 	// Inputs
  6. 	reg x;
  7. 	reg y;
  8. 	// Outputs
  9. 	wire z;
  10. 	// Instantiate the Unit Under Test (UUT)
  11. 	comparator uut (
  12. 		.x(x), 
  13. 		.y(y), 
  14. 		.z(z)
  15. 	);
  16.  
  17. 	initial begin
  18. 		// Initialize Inputs
  19. 	x = 0;
  20. 	y = 0;
  21.  
  22. 	#20 x = 1;
  23. 	#20 y = 1;
  24. 	#20 y = 0;	
  25. 	#20 x = 1;	  
  26. 	#40;
  27.     end  
  28.  
  29. 		initial begin
  30. 		 $monitor("x=%d,y=%d,z=%d \n",x,y,z);
  31. 		 end
  32.  
  33. endmodule
  34.  
  35.  


Now go to the dos windows ( Start -> cmd) navigate to the iverilog\bin directory

C:\> cd iverilog\bin

Compile the program using

C:\iverilog\bin>iverilog -o comparator.vpp comparator.v stimulus.v

If everything goes right, it will not produce any output. If there are any syntax errors it will show some errors.

To see the output of the stimulus, you may like to give the following command

C:\iverilog\bin>vvp comparator.vvp

This shows the following output. 


x=0,y=0,z=1

x=1,y=0,z=0

x=1,y=1,z=1

x=0,y=1,z=0

C:\iverilog\bin>

This completes the basic hello world example of the verilog. Notice that , for simplicity we kept our source file in the same directory as the bin. In practice it is not a good idea. There are two workarounds.

1. Keep all your source files in a separate directory - say /iverilog/src and give the full path name of source files when compiling the program ( this is a bit tedious).

2. Define a path name for the C:/iverilog/bin in your computer's list of environment variables. And then you can give the command iverilog from anywhere in the directory. This is a preferred way of doing the things.

You may want to change the equation to see if the result produced is different.

Here are some examples that you may want to take up before proceeding further.

Exercize



1. Change the code such that it compares two values x and y and gives 1 if x is greater than or equal to y. Write stimulus to verify it.

2. Implement and verify the verilog code for a circuit that has three inputs and one one output. The three inputs represent a binary number ( from 0 to 7) and output is 1 if the value is greater than 5 else it is 0.

In the next page we will learn more about Verilog and its language construct.