Verilog TUTORIAL | Verification


If our code is correct it will produce the result according to the following table

Table: A one bit comparator



Input x Input y Output z
0 0 1
0 1 0
1 0 0
1 1 1


Every verilog implementation goes through extensive verification. How do we verify that the circuit behaves as expected ? We basically provide stimulus to the circuit at its input port and check its output. We change the input and check the output again. We continue doing it till we exhaust all possible inputs. If output under all conditions is as expected, the circuit stands verified.

Here is how a stimulus verification code looks like 

  1. // referencedesigner.com verilog tutorial
  2. // testbench for comparator module
  3. `timescale 1ns / 1ps
  4. module stimulus;
  5. 	// Inputs
  6. 	reg x;
  7. 	reg y;
  8. 	// Outputs
  9. 	wire z;
  10. 	// Instantiate the Unit Under Test (UUT)
  11. 	comparator uut (
  12. 		.x(x), 
  13. 		.y(y), 
  14. 		.z(z)
  15. 	);
  16.  
  17. 	initial begin
  18. 		// Initialize Inputs
  19. 	x = 0;
  20. 	y = 0;
  21.  
  22. 	#20 x = 1;
  23. 	#20 y = 1;
  24. 	#20 y = 0;	
  25. 	#20 x = 1;	  
  26. 	#40;
  27.     end  
  28.  
  29. 		initial begin
  30. 		 $monitor("x=%d,y=%d,z=%d \n",x,y,z);
  31. 		 end
  32.  
  33. endmodule
  34.  
  35.  


We will try to make you understand the code. The code 

`timescale 1ns / 1ps


defines the timescale. It tells that the simulation will run in steps of 1ns and has a precision value of 1ps. We will come back to it later.

We need a way for the stimulus to simulate the input and the output pins of the comparator module. We do this by defining two register variables x and y and a wire variable z as in 

// Inputs
reg x;
reg y;
// Outputs
wire z;


We will discuss more about registers and wires later. The next statement creates an instance of the comparator module. 

comparator uut (
.x(x), 
.y(y), 
.z(z)
);


The following section of the code defines the values of the input at different interval of time. 

initial begin
// Initialize Inputs
x = 0;
y = 0;
 
#20 x = 1;
#20 y = 1;
#20 y = 1;	
#20 x = 0;	
#40		
end


Initially the value of x and y are both 0. At t = 50 ns , we assign the value of x as 1. So at t = 50 ns we have x =1 and y = 0. At t = 60 we assign the value of as 1. So at t = 60 we have x =1 and y =1. So and and so forth. At each step, the value of the out z changes in accordance with the design and this is what we need to verify.

The following code monitor the values of x, y and z at EACH change. 

initial begin
$monitor("x=%d,y=%d,z=%d \n",x,y,z);
 end


It will basically display the values of x, y and z as follows. 

x=0,y=0,z=1 
x=1,y=0,z=0 
x=1,y=1,z=1 
x=0,y=1,z=0


In the next page we will see how to test this code using the simulation with Icarus tool.