Signal Integrity TUTORIAL

Adding Delay intentionally

It is often desirable to add or reduce delay to a clock line with respect to a data line to improve the timing margins. In such case, instead or purposely minimizing skew, we change our objective to add additional delay in the clock line with respect to the data line. To be able to do this we must have a good understanding of the set up and hold timing models of the receiver section of the circuit. We should also have an understanding of the timing relationship at the driver side. If the simulation shows an improvement in the timing margin by use of clock or data line delay adjustment we can implement at the design level.

Fixed delay using the transmission line is the most common form of providing delay at the PCB design level. There is no extra cost involved and it often easy to implement. The drawback of this scheme is that it needs space. At propagation speed of 150 ps per inch, providing 600 ps of delay will need 4 inch of extra length.

The figure below shows a serpentine delay. The spacing between the delay lines is very close.

If the adjacent traces in the serpentine delay are very close to each other, there is a coupling between the traces. This in turn provides an ac return path. As a result the signal travels faster in the serpentine path as compared to the straight path. The effective delay of the serpentine delay is therefore smaller than the corresponding straight trace delay.

If you however space the traces in serpentine delay lines are too far away, it takes too much of PCB space. Keeping them too close has two undesirable effects. The first is the reduction in the effective delay. The second is the creation of plateau at the low and the high levels of the signal. The plateau at the low level can eat up voltage margin.

We must therefore simulate the serpentine traces to take into account the reduction in the effective delay and creation of voltage plate