Miscellaneous SI Topics - Models and Modeling
Every simulator has support for basic models which includes resistors, capacitors, transmission lines, coupled lines, FETs, transistors, junctions to name a few. Many of them have support for the SPICE and ibis models.
SPICE models model a circuit at transistor level. SPICE models contain detailed information about the circuit and process parameters. A single device SPICE model consists of an ascii file with .MOD extension. SPICE has support for standard parts. So, if the device is one of the standard SPICE parts such as diodes, transistors, resistors, capacitors, etc, then it will be represented as a ".model" statement. In many cases the device is made up of combination of many circuits connected in some way. In that case we can represent the circuit as a sub-circuit, and written as a ".subckt" block statement.
Here is an example of the SPICE model for Fairchild 2N5460 P channel FET.
.model J2N5460 PJF(Beta=500u Betatce=-.5 Rd=1 Rs=1 Lambda=10m Vto=-3
+ Vtotc=-2.5m Cgd=2.5p M=.3333 Pb=1 Fc=.5 Cgs=4p Is=90p
+ Isr=800p N=1 Nr=2 Xti=3)
Since it “fits” into the standard PJF fet model of SPICE, all Fairchild semiconductor has to do is to define the parameters of the PJF.
* TL071 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
* (REV N/A) SUPPLY VOLTAGE: +/-15V
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OUTPUT
* | | | | |
.SUBCKT TL071 1 2 3 4 5
*
C1 11 12 3.498E-12
C2 6 7 15.00E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195.0E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100.0E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.200
VE 54 4 DC 2.200
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800.0E-18)
.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
.ENDS
If you know the components and processes inside an IC, you can make your own model by defining the parameters of the individual elements and interconnecting them. If your have your own circuit, e.g., if you are designing your own switching mode power supply using discrete components, and, if you are able to get the spice models of all the components used, you can generate the spice model for your power supply using .subckt statement and interconnecting all the components used.
Vendors of the complex ICs such as processor or mixed signal ICs do have SPICE models with them. However the model contains the proprietary information. Giving out the SPICE model will be equivalent to handing out the proprietary design. Getting the SPICE model for complex ICs is not an option in most cases for designers even if there exists one.
Original SPICE models are highly accurate. One limitation of the full SPICE model is speed of simulation if your simulation needs calculations for several variation of one or more parameter.
The PCB designers do need the models of the ICs to be able to simulate the behavior of the IC. Input/Output Buffer Information Specification or IBIS was developed to solve the problem of providing the models without giving out the proprietary information. IBIS model is a behavioral model. It is not 100% real model as it does not contain the actual hardware device models. It rather tends to provide the information in the form of tables. I/V output curves, rising/falling transition waveforms, and package parasitic information of the device.
Where does this lands a PCB designer to ? Instead of directly starting the IBIS or SPICE model, you can try to get some basic information about the driver and the receiver. What is the rise time ? What is the series resistance for the voltage source driver ? What is the parasitic capacitance of the IC.
For example a typical driver can be modeled as a voltage source with 20 ohm series resistance. The stimulus is a ramp voltage modeled as a piecewise linear waveform with rise time of 500 ps and fall time of 500 ps. The receiver can be modeled with a simple resistance connected to ground if it is a parallel termination. We should include parasitic capacitance in the model. In between the transmitter and the receiver, we can include the model of the PCB trace using the model of a transmission line.
Once you have this setup, try to run simple simulation and compare the results against the results of the simulation with supplied ibis or spice mode. If they correlate, your assumption about simplification of the models was correct. An advantage of this method is that you get an intuitive idea of the drivers and receivers. You may still like to simulate finally with the vendor supplied models once you are about to sign off the design rules.
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