Miscellaneous SI Topics

Package Model

The model of a complex IC will usually consist of two parts – one is the model of the silicon itself and other is the model for the traces interconnecting the silicon to the pins of the package.

To understand package and the parasitics, take a look at the following IC picture. The picture is for an AMD processor. This particular processor is a multi-chip module which means that there are two silicons on a single package. The traces from the silicon cover a finite amount of trace when coming from silicon to the BGA pins of the IC. This path has parasitic element associated with it. IBIS models them as and RLC matrix.



Figure - A processor IC showing silicon and package

A section of the IBIS model for the package looks as follows

<[Package]
variable        typ           min         max
R_pkg           0.17          0.07        0.33
L_pkg           1.95nH        1.15nH      3.12nH
C_pkg           0.52pF        0.29pF      0.87pF

When doing simulation, we must not forget to take into account, the package model. If higher accuracy is desired, you can insist upon the transmission line model of the package from vendor. The ibis RLC matrix models the traces as lumped element. The length of the traces from the package pins can be as high as 0.8”. The lumped element model is typically good up to 1 GHz if the trace lengths are less than about 0.6”. For higher edge rates and high frequencies, modeling the package parasitic as transmission line in place of the lumped element will be a more practical approach. The simple RLC approach also does not model the trace to trace coupling and therefore can not simulate cross talk.

With all its limitation, RLC matrix gives a good approximation for frequency components up to 1 GHz. Never omit it in your final simulation. The RLC matrix should also be used if you are trying to implement length matching for the positive and negative traces of very high speed differential signals. Ideally, we should calculate the difference in the electrical length of the positive and negative traces at the transmitter and the receiver in the silicon packages. This difference in the electrical length in packages should be balanced by the traces on the PCBs. If the trace length of the positive signal is higher than the negative signal in the silicon package then we should make the trace length of the positive trace in the PCB shorter. One drawback of this scheme is that the newer version of the package may have different lengths of the traces. Practically, the differences are very small and can be ignored.


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