Verilog Half Adder Example on Spartixed


We will now implement a half Adder that takes in has two 4 bit inputs and gives out sum and carry. The sum generated is also 4 bit and is displayed on the 7 Segment Display. The generated carry is displayed on the LED.

We make use of the Hex to 7 Segment coder we wrote and verified earlier.

So here goes the code - it is short and simple 



//Spartixed board from referencedesigner.com
// Half Adder Example
module halfadder(
    input [3:0] a,
    input [3:0] b,
 
    output [6:0] out,
	 output ssegselect,
	 output led2 // For Carry
 
    );
 
	 wire [3:0] sum;
    wire  carry ; // Though we need only 1 bit - we are doing BCD
 
  assign {carry,sum} = a+b;
  assign led2 = carry; 
 
 hex_to_7segment h1( sum, ssegselect, out);
 
endmodule


You will have to use the hex to 7 segment display module we developed earlier and is a part of this project. 



module hex_to_7segment(
    in ,select, out 
  );
 
input [3:0] in;    // Input from DIP Switches
output select;  
output [6:0] out;
 
parameter A      = 7'b0000001;
parameter B      = 7'b0000010;
parameter C      = 7'b0000100;
parameter D      = 7'b0001000;
parameter E      = 7'b0010000;
parameter F      = 7'b0100000;
parameter G      = 7'b1000000;
 
 
assign select = 1'b1; // Which of the the 3 seven segments we wish to display
 
assign out =
    (in == 4'h0) ? A|B|C|D|E|F : // Display 0
    (in == 4'h1) ? B|C : // Display 1
    (in == 4'h2) ? A|B|G|E|D : // Display 2
    (in == 4'h3) ? A|B|C|D|G : // Display 3
    (in == 4'h4) ? F|B|G|C : // Display 4
    (in == 4'h5) ? A|F|G|C|D : // Display 5
    (in == 4'h6) ? A|F|G|C|D|E : // Display 6
    (in == 4'h7) ? A|B|C : // Display 7
    (in == 4'h8) ? A|B|C|D|E|F|G : // Display 8
    (in == 4'h9) ? A|B|C|D|F|G : // Display 9
    (in == 4'ha) ? A|F|B|G|E|C : // Display A
    (in == 4'hb) ? F|G|C|D|E : // Display B
    (in == 4'hc) ? G|E|D : // Display C
    (in == 4'hd) ? B|C|G|E|D : // Display D
    (in == 4'he) ? A|F|G|E|D : // Display E
    (in == 4'hf) ? A|F|G|E : // Display F
        4'bz;
 
endmodule



The video shows the result when it is implemmented on Spartixed board.



Following ucf file is used. 



NET "a[3]" LOC = P27;
NET "a[2]" LOC = P26;
NET "a[1]" LOC = P24;
NET "a[0]" LOC = P23;
 
NET "b[3]" LOC = P33;
NET "b[2]" LOC = P32;
NET "b[1]" LOC = P30;
NET "b[0]" LOC = P29;
 
NET "led2" LOC = P131;
 
NET "out[0]" LOC = P5;
NET "out[1]" LOC = P141;
NET "out[2]" LOC = P16;
NET "out[3]" LOC = P21;
NET "out[4]" LOC = P22;
NET "out[5]" LOC = P2;
NET "out[6]" LOC = P15;
 
NET "ssegselect" LOC = P12;




Suggested Exercises

1. Test the results of the code by diplaying the difference of two numbers and explain the result.