Timing Relationship between Signals
CHAPTER 11.2 Timing Relationship between Signals
The signal launched at one end of the PCB trace takes finite amount of time when traveling from one end to another end of the trace. The signal typically takes 150 ps to travel 1 inch of trace. If your trace is 8 inches long, it will take 1200 ps to travel from one end of the trace to the other end. In many buses, clock and data need to preserve a definite timing relationship. If the receiver captures data at the rising edge of the clock, then the data must arrive and become stable slightly before the rising edge of the clock. The time before which the data must be valid before the rising edge of the clock is called setup time. Consider for example, a receiver having a setup time requirement of 1200 ps. It means that the data must arrive at least 1200 ps before the arrival of the clock signal. A transmitter drives data at t = 0 ps and the rising edge of the clock at t = 1500 ps. If the lengths of the data trace and the clock trace are equal on the PCB, data will arrive 1500 ps before the rising edge of the clock. Since the data arrives before the setup time of the clock, it will be correctly captured by the receiver. Now consider an extreme case where data trace is made very long. So long so that it takes data signal 500 ps more than it takes to the clock signal to arrive at the receiver. This means that the receiver sees data signal arriving just 1500 ps – 500 ps = 1000 ps before the clock signal. The receiver, however requires that the data be available and stable at least 1200 ps before the clock signal. The PCB design error like this can lead to the failure to meet set up time requirement of the receiver. This can be a cause of intermittent failure. PCB designers need to ensure that the delay caused in the PCB routing does not lead to the undesirable timing relationship between the clock and the data signals.
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