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VERILOG GOTCHAS

July 11th, 2015

Gotcha is a legal language construct that does not produce intended result, in hardware language. Most gotchas simulate but do not produce intended result. For example if we write a=b instead of a==b in program the results can be different without any compilation errors. It can be disastrous if not found before the product is being shipped. So as an engineer should be careful and be able to detect these gotchas especially in large designs.

There are sets of reasons behind gotchas in languages like verilog\system verilog

[ A side note - You can choose various hardware tools and review them here . ]

- Verilog and System verilog are similar to C\C++,so most gotchas are shipped from these languages to languages like verilog and SV.
- Way of execution are different for different EDA tools for verilog and system verilog standards
- Operations depend on language rules

Let us understand by one example using verilog for 4 to 1 Multiplexer

module Mux4_1 (out,s1,s0,i0,i1,i2,i3);
output out;
input i0,i1,i2,i3;
input s1,s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
begin
case ({s1,s0})
2'b00:out=i0;
2'b01:out=i1;
2'b01:out=i2;
2'b11:out=i3;
default:out=1'bx;
endcase
end
endmodule

So look at the above example of 4to1 Multiplexer using verilog and we can clearly see that 2’b01 has been repeated twice which is not desirable but still the program is syntactically correct and will simulate but won’t give desired result.

gotcha1

Let us understand one more gotcha using below example

`timescale 1ns/100ps
module Tb();
reg clock;
integer no_of_clocks;
parameter CLOCK_PERIOD = 30;
initial clock = 1'b0;
always
begin
#(CLOCK_PERIOD/3.0) clock = 1'b0;
#(CLOCK_PERIOD - CLOCK_PERIOD/3.0) clock = 1'b1;
end
initial no_of_clocks = 0;
always@ (posedge clock)
no_of_clocks = no_of_clocks +1 ;
initial
begin
#50000;
$display ("End of simulation time is %d , total number of clocks seen is %d expected is %d",$time,no_of_clocks,($time/5));
$finish;

In the above verilog program $display might execute before assignment operation, it all depend on tool which you are using but if you use $strobe instead it will be executed always at last which will always produce desirable result.

gotcha2

Now let us figure out some precautions to avoid gotchas in verilog
- Avoid misplacing semicolon in statement like end or join
- Should know whether operator is self determined or context determined
- Undeclared vector infers 1bit wire
- Literal syntax should be followed
- Sign extension rules should be followed
- Declaration of variables in continuous assignment
- Sensitivity list in always block of combinational logic

So now I hope it is clear, what are gotchas?Just keep the programming rules as much as you can to avoid them and everything will be fine. So we have seen so far that a language like verilog which appears very simple is not simple at all as it contains some hidden features.

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