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Verilog Initial block synthesis

In Verilog, Initial blocks are used in test benches. There may be one or more than one initial block all running simultaneously right at the beginning.

Can initial block be also used in synthesis. For example, you may be tempted to write the code as follows

module dff_not_synthesizable(clkin,q,d);
input clkin,d;
output q;
reg q;

initial  // Not synthesizable

begin
 q <= 0;
end 

always @ (posedge clkin)
begin
 q <= d;
end 

endmodule

We are trying to make sure that initially the output is 0 using the initial statement

begin
q <= 0; end However, the code will not synthesize. We should be using a reset input instead, to make make initial value of the output of the D flip flop low at the time of reset. Initial blocks are non synthesizable blocks. Why the hell then is it included in Verilog ? To confuse the students ? Well, generating synthesizable code is not the only purpose of Verilog. A lot of effort goes on in verifying the code that is synthesizable. And hence we need a lot of other constructs and initial block is one such construct. The $display, $monitor etc are other such constructs that will not synthesize, but will help in testing the code.

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