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Verilog Xilinx Evaluation board - Getting started

September 5th, 2015

Once you have gone through the initial coding and verification in verilog ( or for that matter in VHDL), it is time to download the code in a Verilog evaluation board ( or your actual designed board, as the case may be) to the real working code. In this blog we will get you started with setting up an environment to download the .bit file generated from Xilinx tool and see its function. We will be using the JTAG connector and will download the code directly in Xilinx chip and not to any external EEPROM. The XC6SLX9 - 144 Pin version will be used to demonstrate this example.

This verilog code is as follows.

module led(
    input switch,
    output led
    );
	 
assign led = ~switch;

endmodule

The module does nothing but turns the LED on or off depending upon if the switch is pressed or not. The one thing that we need to define is - which pin will be switch and which one will be LED. To do this using UCF ( User Constraint File) File. The contents of this file is as follows

## This file is a general UCF FIle
# This UCF file is for 144 Pin Xilinx XC6SLX9 chip 

NET "switch" LOC = P124;
NET "led" LOC = P127;

In UCF File, lines that start with # are treated as comment. The pin and its associated name in a module is defined using NET as in

NET "switch" LOC = P124;

If the part is a BGA part the actual pin number is associated. For QFP type parts, P is appended before the pin number.

If everything goes well, double clicking the "implement design", implements the design. Finally, clicking the Generate programming file will generate the bit file that can be used to download the bit file to the evaluation board.

To actually program the Xilinx Chip, connect the USB Platform Cable to your computer and connect the FPGA Cable to the evaluation board. The computer may like to install the driver if it is the first time you have plugged in platform cable.

1. Click on Configure Target Device. It will bring you to impact window.

2. Double click the “Boundary Scan” icon to launch the programming interface, and right click on the blank area. Just like the following picture, select “Initialize Chain”.

3.The JTAG cable tries to find all the devices in JTAG chain and show them in the window. Press “No” and then “Cancel”.

4. Right click on the FPGA device. In your case it is XC6SLX9. Select “Assign New Configuration File”.

5. Find the *.bit file, and choose it in the window.

6.Right click on the FPGA device, and select “Program” and “OK”.

7. The “Program Succeeded” symbol will be printed on your screen if every thing is OK, and then FPGA begins to work.

Note that the program is lost once it is powered off.

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