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Verilog code for 7 Segment LED Display

September 18th, 2015

We will publish verilog code that will display sequence of digits from 0 to 9, something similar to the figure below.

7-segments_Indicator


module mode10(
input clk,
input reset,
output leda,
output ledb,
output ledc,
output ledd,
output lede,
output ledf,
output ledg
);
reg [26:0] count;
reg [3:0] counter;
reg [6:0] seg_data;
always @(negedge clk or negedge reset)
     begin
      if (reset ==0)
	  begin
       count<=27'd0;
	   counter <= 4'b0;
	  end	
	   else if (count==27'd50000000)
	    begin
		count <=27'd0;
		if (counter < 9) counter <= counter +1;
		else  counter <= 0;
		end
      else 
         count<=count+1;
     end
always @(counter)
case (counter)
4'b0000:seg_data=7'b1111110;
4'b0001:seg_data=7'b0110000;
4'b0010:seg_data=7'b1101101;
4'b0011:seg_data=7'b1111001;
4'b0100:seg_data=7'b0110011;
4'b0101:seg_data=7'b1011011;
4'b0110:seg_data=7'b1011111;
4'b0111:seg_data=7'b1110000;
4'b1000:seg_data=7'b1111111;
4'b1001:seg_data=7'b1111011;
endcase

assign leda=seg_data[6];
assign ledb=seg_data[5];
assign ledc=seg_data[4];
assign ledd=seg_data[3];
assign lede=seg_data[2];
assign ledf=seg_data[1];
assign ledg=seg_data[0];

endmodule  

It is assumed that the clock frequency is 50 MHz. The following statement counts for 1 second duration

 
else if (count==27'd50000000) // 50 MHz clock
	    begin
		count <=27'd0;
		if (counter < 9) counter <= counter +1;
		else  counter <= 0;
		end

If the clock input is, say, 1 MHz, the counter will scale down accordingly.

 
else if (count==27'd50000000) // 50 MHz clock
else if (count==27'd1000000) // 1 MHz clock
else if (count==27'd50000) // 50 KHz clock

Test Bench

The following test bench can be used to test the code.

`timescale 10us/10us
module modetentb;
output reg clk;
output reg reset;
input leda;
input ledb;
input ledc;
input ledd;
input lede;
input ledf;
input ledg;
mode10 mode(clk,reset,leda,ledb,ledc,ledd,lede,ledf,ledg);
initial
clk=1'b0;
always
#1 clk=~clk;
initial
     begin
	 $monitor($time,"reset=%b,leda=%b,ledb=%b,ledc=%c,ledd=%b,lede=%b,ledf=%b",reset,leda,ledb,ledc,ledd,lede,ledf,ledg);
               reset=1;
            #1 reset=0;
            #1 reset=1;
			
            #300000 $finish;
     end	    
initial
      begin
      $dumpfile ("modetentb.vcd");
      $dumpvars (0,modetentb);
      end
endmodule

It is assumed that the clock input is 50 KHz, and the counter is scaled back accordingly in the main code.

else if (count==27'd50000) // 50 KHz clock

Once the verification is over, it is time to compile the code and download it to the evaluation board. We use the actual count value for generating bit file and download.

else if (count==27'd50000000) // 50 MHz clock

In the main verilog code, you could also replace

assign leda=seg_data[6];
assign ledb=seg_data[5];
assign ledc=seg_data[4];
assign ledd=seg_data[3];
assign lede=seg_data[2];
assign ledf=seg_data[1];
assign ledg=seg_data[0];

with shorter code, like

assign {leda, ledb,ledc,ledd,lede,ledf,ledg}=seg_data[6:0];

assign leda=seg_data[6];

Uncategorized

  1. Raita
    April 9th, 2019 at 10:53 | #1

    Test bench isnt Working
    . It shows error. Hoe to solve this? It says module command Isn't functioning .

  2. sahar syed
    May 16th, 2019 at 09:08 | #2

    small brackets missing in test bench..and a semicolon

    module modetentb(
    output reg clk,
    output reg reset,
    input leda,
    input ledb,
    input ledc,
    input ledd,
    input lede,
    input ledf,
    input ledg
    );

    @Raita

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