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Posts Tagged ‘verilog’

Scaling Clock frequency for faster simulation in Verilog

September 17th, 2015

If you have a faster system clock, say, at 50 MHz that needs to generate counter at a much slower speed, say 1 Hz, the simulation may not be efficient. The counter or clock divider used will be very slow and will generate a very big file to generate waveform.

Consider the simple case where we are generating a 1 Hz time from a 50 MHz clock. The time period corresponding to the 50 MHz clock will be 20 ns ( 1/ 50 MHz = 20 ns). The half clock period will be 10 ns. A typical timescale directive and the statement to generate clock will be

`timescale 10ns/10ns
.
.
initial
clk=1'b0;
always
#1 clk=~clk;

If the code uses a counter for 1 second, then typical code will be

reg [26:0] count;
reg [3:0] counter;
always @(negedge clk or negedge reset)
     begin
      if (reset ==0)
	  begin
       count<=27'd0;
	   counter <= 4'b0;
	  end	
	   else if (count==27'd50000000)
	    begin
		count <=27'd0;
		if (counter < 9) counter <= counter +1;
		else  counter <= 0;
	end
      else 
         count<=count+1;
     end

This will increase the "counter" value in 1 second interval. However, if you try to simulate this, the test bench need to run for a very long count value to display values of counter. Under such scenario, it me a be better idea to scale down the input clock. For example we may assume an input clock to be 50KHz in place of 50 MHz ( a factor of 1000).

The count value in this case can be changed from

 else if (count==27'd50000000)
	    begin
		count <=27'd0;

to

 else if (count==27'd50000)
	    begin
		count <=27'd0;

At simulation, we change the timescale from

`timescale 10ns/10ns

to

`timescale 10us/10us

Again applying a factor of 1000. The result of this exercise is that our end result is same. When we scale the clock from 50 KHz to 50 MHz, we scale up the actual counter factor to 1000.

slow-fast-clock-inverilog

Notice the period of clk used in this simulation.

slow-fast-clock-inverilog1

It generated a vcd file that had a size of 6 MB. If we had not scaled it, its size would have been 6000 MB ( approx). The simulation time will be 1000 times more.

As an exercise, we ask the reader to write a verilog code that has 50 MHz clock input and it will count in interval of, say, 1 second. Try to simulate the code.

This exercise and its solution will be published with a Xilinx evaluation board to be soon released. The full code will be published shortly. For a complete verilog tutorial, please see here .

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Verilog Initial block synthesis

May 4th, 2015

In Verilog, Initial blocks are used in test benches. There may be one or more than one initial block all running simultaneously right at the beginning.

Can initial block be also used in synthesis. For example, you may be tempted to write the code as follows

module dff_not_synthesizable(clkin,q,d);
input clkin,d;
output q;
reg q;

initial  // Not synthesizable

begin
 q <= 0;
end 

always @ (posedge clkin)
begin
 q <= d;
end 

endmodule

We are trying to make sure that initially the output is 0 using the initial statement

begin
q <= 0; end However, the code will not synthesize. We should be using a reset input instead, to make make initial value of the output of the D flip flop low at the time of reset. Initial blocks are non synthesizable blocks. Why the hell then is it included in Verilog ? To confuse the students ? Well, generating synthesizable code is not the only purpose of Verilog. A lot of effort goes on in verifying the code that is synthesizable. And hence we need a lot of other constructs and initial block is one such construct. The $display, $monitor etc are other such constructs that will not synthesize, but will help in testing the code.

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