Signal Integrity Topics
I saw that following topics being covered in Terry Fox SI Class
PCB Stack-up… What constitutes a proper stack up? What is the purpose of various layer combinations? To become a proficient high speed system designer you must become stack-up connoisseur who can explain the purpose of each layer and the ramifications of changing or deleting a layer.
Power Deliver Network Design… A typical FPGA/CPU to memory interface power deliver systems must produce nearly an amp of current in a sub-nano second period. In otherwords, the power delivery network must work from DC to well over 1 GHz. This is not just a “put the capacitor close to the power pin” type of problem. Understanding power delivery requirements and solutions are fundamental building blocks in any high speed design.
Trace Routing, Return Current Control, and Via Placement… What constitutes a proper high speed trace topology? Which layers are routing pairs? … Why are they routing pairs? Missing the routing on a single high speed trace can result in a board spin.
Ground Bounce / Simultaneous Switching Noise… What is it? Why should you care? How do you control it?
Ringing, Cross Talk, EMI, Ground Bounce, and Termination… These are tightly related. Fix one and the rest tend to fall into order. Miss one and you may need to spin the board.
Connectors… What signals need to be in the connector and where should the connectors be located for best Signal Integrity and EMI performance?
Analogue-Digital Interface Design and Split Planes… This topic is the source of a tremendous amount of engineering folk lore. Sadly much of the folk lore is wrong causing all kinds of nasty problems.
Signal Loading, Timing Loops, and Noise Budgets… Plan for success and you have a reasonable chance of making it. Thinking happy thoughts and hoping for the best is not a professional design skill.
The classical sources of EMI and methods to stop it at the source … This class takes the approach that most of us need to build systems which are packaged in plastic boxes and have long wires extending from those boxes. If you do not stop EMI at its source, there is no place to hide. This class teaches the student how to prevent EMI generation at its source.
Technologies specifically addressed… CMOS clocked parallel buss (SDRAM or DDR2), SERDES (PCI Express), differential LVDS, and mixed signal analogue digital boards
You may like to look at the SI tutorial at SI Tutorial. The book “Signal Integrity for PCB Designers” by Vikas Shukla is also a good reference.