Removing unused internal pads from PCB Via
If you are using a via on a high speed net, chances are - it has excessive capacitance. The main source of the excess capacitance is the coupling between the via pads and the nearby power plane.
One quick way to reduce the via capacitance is to reduce the size of the pad. You start with the minimum drill size, which is typically 8 mils for most inexpensive PCB Fabrication processes. Now you need a minimum 4 mil trace for common inexpensive process which sets the minimum Via diameter size as 16 mils.
Even with the reduced pad size, the via is capacitive. The next step to reduce the capacitance is to increase the Antipad size. If you do not specify the antipad size, the separation between the via and the power plane is determined by the design rule of clearance between power plane flood and the nearest trace. For example if this clearance is set to be 4 mils, the diameter of the antipad can be assumed to be 24 mils or 8 mils more than the pad diameter of 16 mils. Typically if the antipad diameter is set to be 12 mils more than the pad size, we get reduced capacitance from via.
One final important way of reducing the via capacitance is the by removing the internal unused pads from via. These unused pads are more popularly called non functional pads. In a typical design, the pads are almost always present in the top and the bottom layers. Simplified via design has pads connected to all internal layers. So if a trace is going from top layer to bottom layer, the internal via pads are present even if not used. These internal unused pads add to the via capacitance. If you care for high speed designs, it is a good idea to consider removing these internal pads from the via. The separation between the via barrel and the power and ground plane increases, reducing the via capacitance.
You may extend the same concept by defining a new via from top layer to an internal layer. For example if you have an 8 layer board and you you are jumping from layer 1 to layer 6, you may remove via pad from all layers, except from 1( top) , 6 and 8 ( bottom). Each internal signal layer will require separate via definition(s).
I am not a manufacturing expert, but there is one aspect that is certain - removing the Non Functional pads, does reduce the separation between the pads and the power plane and thereby reduces the chance of short, especially in the dense BGA areas. The PCB house, therefore, like to remove the Non Functional pads and potentially improve the yield.
There have been other discussion about the via barrel cracking and there are discussion about how the additional pads help keeping the barrel together. It appears that removal of the non functional pads does not create any disadvantage from manufacturing, yield or long term reliability perspective.
Via Back Drill
The removal of the Non Functional pad works at the design level ( or the gerber level). Another way to reduce the additional Capacitance is back drilling the pads. If a trace is going from Layer 1 to Layer 3 in a 8 Layer PCB, we have an extra stub from Layer 3 to Layer 8. Even if we remove the internal non functional pads, we have pads on layer 8. Back drilling is the process to remove the extra stub and the pad. This serves dual purpose - removal of the pad and the removal of the extra stub.
How about Non Functional Pads on Via for Power connections
Power connections are a totally different from high speed. In via for power plane, we wish to keep the length of the via drill to the minimum and we wish to keep capacitive coupling ( between power and ground ) high. The pad size in power via should be kept large to provide more capacitance. There is little discussion about the design of the via for delivering power nets. The design of via for the power nets will be guided by two basic principles - reducing the via drill inductance and more capacitive coupling between power and ground nets.
We expect your comments on this serious discussion.
By Vikas Shukla
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