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PCB Via for High Speed Design

October 27th, 2015

The topic of PCB via and its capacitance with reference to the High Speed design was briefly discussed in the book Signal Integrity for PCB Designers, here . The topic requires a little more in depth analysis in 1 GHz and beyond range. Here are key points about via

1. The Via is predominantly capacitive. The top and the bottom pads of the via are main sources of the capacitance. Also the inner pads are electrically coupled with ground and power planes give additional capacitance. We should therefore try to minimize the size of the pad. It will require keeping the drill size to bare minimum. In most PCBs, the minimum drill size is of the order of 8 mils. Since the typical minimum trace width is 4 mils, the diameter of the pad is typically 16 mils at the minimum.

2. Enlarging the size of the antipad reduce the coupling of the pad and the drill with the ground layer and reduces the capacitance. For exact size of the antipad, a 3D simulation software should be used.

3. The drill length connecting the top and the bottom pad is predominantly inductive. This creates the inductive discontinuity. The length of this inductive discontinuity is typically 0.063 inch, which corresponds to 10.7 ps, assuming the speed of propagation in inner layer to be 170 ps per inch.

4. The inductive discontinuity starts playing role, when the rise time of the signal is less than 10x the electrical drill length of via. This rise time corresponds approximately to 107 ps. Whenever, time the rise time is less than about 100 ps, start considering the inductive discontinuity due to via. The lower the rise time, the more marked is the inductive discontinuity.

5. As a first order approximation, the via can be modeled as a pi circuit with two capacitor and one inductor as shown in following circuit.


The two capacitors correspond to the top and the bottom pads and the inductor correspond to the drill from top to the bottom.

6. As a first order the capacitance of the via can be given by the following formula.



εr = relative dielectric constant,
D1 = diameter of the via pad in inch,
D2 = diameter of the anti-pad in inch,
T = thickness of the PCB in inch,

7. According to the formula, increasing the Antipad size D2, and reducing the via diameter D1 reduces the via capacitance.

8. You can use the via capacitance calculator for a first order via capacitance calculator.

9. The above formula assumes that the inner ground layers are continuous and forms kind of a coaxial surface around the via drill. In that sense, it over estimates the via capacitance. In other words, it assumes presence of infinite number of ground planes. It also overestimates the effect if the anti pad. The formula also assumes that the size of the pads are same in the outer as well as the inner layers.

10. As a gross approximation, the via inductance can be estimated as


d = diameter of the drill hole in inch
h = thickness of the PCB ( or via length) in inch

11. The via inductance does not take into account any return path for the current. If there is a nearby via, the inductance of the loop will be substantially smaller.


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