Never Rely completely on automatic Design Rule tester
In 2002, I was in charge of the Signal Integrity team, designing AMD based server motherboard. The motherboard consisted of many high speed signals including DDR2, PCI – 133 MHz, HyperTransport , Gigabit Ethernet. Serial ATA and others.
The responsibility of the signal integrity team was to conduct all the simulations and hand over the design rules to the Layout team. The layout team was responsible for ensuring that the rules are followed. We finally had a check list which a signal integrity engineer will fill out and sign out. The Signal Integrity engineer used to check the layout file, the length report and cross check it against signal integrity rules. If there was anything that potentially violated the signal integrity rules, it will be communicated to the layout engineer and to the team manager to take corrective action.
After several back and forth and design check, cross check, layout modification, the design was released for fabrication. The assembled board arrived after a couple of week. It was in the hands of the debug team and the BIOS team for few days before it came into my hand for signal integrity tests. I ran many tests, taking scope shots, running frequency and voltage margin tests , correlating my simulation results with the observed results. Everything looked as expected except one thing – the Gigabit Ethernet. The Gigabit Ethernet test consisted of sending a large file over a 25 meter long Ethernet cable and checking it at the receiver. It looked fined except that the software reported occasional errors in the reception. We checked and cross checked and it was not clear to me if this was a software issue or a hardware issue. We kept fighting and I questioned the methodologies used by the software engineers. I was obviously confident about my own methods and did not think that anything could be wrong at the hardware design end. We had taken care of the differential impedance calculations, we had maintained the length balance between the positive and negative ends of the differential signaling. I was confident of my knowledge about the differential signaling because of my extensive experience with HyperTransport bus.
Just out of curiosity, I opened the layout file one day when I was about to leave office, to check the routing of the differential pair of the Gigabit Ethernet circuit. I checked the lengths of the positive and negative of the signal pairs. They were matched to within 10 mils. Then I started looking if any asymmetry could exist in the differential pair. Suddenly, I found the issue and jumped off my seat. The figure below shows the way the differential pair signal was laid out by the layout person.
Figure 1 : Routing of Differential Signal with matching length
On one of the two signals there was a circular stub, that was taken into account when calculating the length of the differential signal. To match the signal lengths the other signal was stretched near the receiver. In the length calculation, the layout tool took into account the length of the circular stub. Electrically, however, the first trace was shorter. That was enough to cause the kind of error that we were seeing.
We made some fine knife cuts and joints and the error was gone.
I learnt that even though we could use the automatic checking script we should visually check all critical nets with a critics mind. It does not take that long to find errors.