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Minimal Hardware Configuration for XC6SLX9-2TQG144C

November 27th, 2015

When you are bringing up a new processor or FPGA board for the first time, you want to know the minimum set of hardware required to make the board boot. In the post I will go through the minimal set of components required to boot the Xilinx's popular XC6SLX9-2TQG144C , the 144 Pin Spartan 6 FPGA.

If you are releasing your new design you need to double and triple check these pins. A single mistake and it will be hard for you to proceed any further.

1. Power and Ground

The Xilinx XC6SLX9-2TQG144C requires three power supplies

VCCINT - This is the Power-supply for its internal core. The Pin numbers are 19,28,52,89,128. The typical power suppy is 1.2V. And yes, do not forget at least 4 decoupling capacitors ( 1 on Pins 19,28, one each on 52, 89 and 128).

VCCO - These are power supply pins for Output driver. Each of the 4 banks can have there own VCCO. In a typical design, these will all be at 3.3, assuming you are using 3.3V for output supplies. Each bank has 2 to 3 pins. Each of the 4 banks are along the 4 sides of the TFFP package. Again, it will be good to have 2 to 3 decoupling caps along on each of the 4 banks.

VCCAUX - Power supply pins for Auxilliary Circuits are typically at 3.3V

The figure below shows the section of the circuit with power supply.


2. Configuration Pins

Once you have the power supplies done correctly, you need to ensure that the configuration pins are done correctly. This circuit shows part of the schematics for configuration.


CMPCS_B_2 - - This pin ( Pin # 72) is reserved for Xilinx and is recommended to be left unconnected or connect High ( to VCCO). The best thing to do about this pin is to leave it unconnected. If you connect it to ground, you will see unexpected results.

SUSPEND - - This pin ( Pin # 73) - This is an Active high pin, to make the SPARTAN 6 go in power saving suspend mode. If you are not using this feature, connect this pin to ground.

PROGRAM_B_2 - Active-Low reset to configuration logic ( Pin #37). If for example, you are using an external SPI memory to load configuration, then making this pin low will reload the configuration. In the schematics below, this pin has been pulled high with a 0.1uF Cap for giving it a little time after power on to go high. A switch allows manual reloading of configuration. Do not press this switch when you are debugging with JTAG - you will have to reload the JTAG program.

Configuration Pins M1 and M2 - The Configuration Pins M1 ( Pin # 60) and M0 ( Pin #69) determines which and how the device will boot. When you are downloading your software using JTAG, these pins are dont care. In a typical configuration when you connect a 4 bit wide SPI Flash to boot the board, M1 will be 0 and M0 will be 1. The table shows other possible configuration ( the table is taken from Xilinx Datasheet).


Once you have done your power supplies correct and your configuration pins are done right you want to make sure that the JTAG Pins are connected properly. These Pins are TMS, TCK, TDO and TDI ( and of course the 3.3V and GND to the JTAG emulator). If these are done correctly, you should now be able to connect a JTAG programmer and be able to communicate with your SPARTAN 6.

Booting Standalone with SPI EEPROM

While the pins listed above will allow a JTAG to connect to your board, it will not be able to boot on its own. You will need to hook a SPI Flash ( and of course, program it with configuration bits) to be able to do that. The circuit shows the minimal configuration for the same.


Also make sure that you have a Clock on its Clock input Pin ( Pin # 55).


This post was prompted by the design of Spartan 6 Evaluation board for learning Verilog . The board is in my hand and is undergoing bring up and testing. Pin 90 ( that was supposed to be connected to VCCAUX) was connected to VCCINT, and that created board bring up issue. Stay tuned for more details.

Vikas Shukla

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  1. tariq khan
    September 27th, 2016 at 05:35 | #1

    please tell me about the LCD program in vhdl

  1. January 6th, 2016 at 20:37 | #1