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Gigabit Ethernet validation

October 9th, 2015

Once you have taken care of the high speed routing rules for Gigabit Ethernet , it is time for the electrical validation test of the Gigabit Ethernet. We will cover the steps involved in the electrical validation of the Gigabit Ethernet. The freescale i.mx6 board with KSZ9021RN chip will be used as an example ( to show test mode settings), but it should be similar for other test scenario.

The Gigabit standard defines of four test modes for testing. These modes can be set by writing to bits 13 to 15 of Control register 9.

Setting Test mode in Freescale i.MX6

The test mode for the Phy chip KSZ9021RN can be set by stopping the boot of the processor at u-boot. Following mii commands can be used to read or write the control registers.

mii device //set current device
mii info //display MII PHY info
mii read //read MII PHY register
mii write //write MII PHY register

Note that there is a bug in freescale i.MX6 uboot source code that prevents the execution of this code.

Test Mode 1

In test mode 1, all four pairs, transmit signals in a predefined manner. This pattern in captured in the following figure.


The point A in the signal correspond to +2 level. In the test signal fist a +2 level is sent and is followed by 127 duration of 0 Level, and is followed by a -2 Signal, represented by B. Then again 127 duration of 0 and then +1 level ( shown as C), then again 127 0s followed by -1 Level ( shown by D).

We then measure the levels at A, B, C and D. The measurement should conform to the following specifications.

1. The absolute values of the peak of the waveform at points A and B shall fall within the range of 0.67 V to 0.82V.
2. The absolute values of the peak of the waveform at points A and B shall differ
by less than 1%.
3. The absolute values of the peak of the waveform at points C and D shall differ
by less than 2% from 0.5 times the average of the absolute values of the peaks
of the waveform at points A and B

The test fixture is used to terminate the Transmitter pairs. It consists of terminating the transmitter pair with two 50 Ohm resistors with center of these two resistors connected to a signal generator. The signal generator transmits a
sine wave with specified frequency and amplitude (1.4 V peak to peak @ 31.25 MHz, in the above case). The purpose of the disturbing signal is to simulate the presence of a remote transmitter.

A high impedance differential probe is used for measurement and a filter is placed between the test point and the probe point. A typical test fixture is shown here.

Template Test

The waveforms at Points A, B, C, D, F, and H have to fit in defined shape (templates). This is measure after making the signal go through a 2-MHz high-pass filter. It is also normalized according to rules described in sub-clause of IEEE Standard 802.3-005. The High speed filter and the normalization step can be done in some of the digitizing oscilloscopes that support these functions.

A typical normalized wavform along with the template is shown in figure below.


Droop Test

Droop test is performed on the long strings of the "+2" and "–2" symbols. Referring the first figure above the voltage droop is measured from point F (minimum point at the start of "–2" symbol string) to point G (500 ns after point F) as well as from point H (maximum point of the waveform as indicated in Figure 3) to J (500 ns after point H).

The template test and the Droop tests are performed in test mode 1.

Test Mode 2

The test signal in mode 2 consist of alternating "+2" and "–2" symbols and is timed to a 125 MHz timing clock called the TX_TCLK. The test mode 2 used device's own 125 MHz Transmit clock..

Test Mode 3

Test mode 3 is same as test mode 3, except that it uses a recovered clock from the data transmitted by a Link partner in Master mode.

Jitter Test

The Clock signal in test mode 2 and test mode 3 is analyzed for jitter measurement. It should be within the specified specification. ( To be updated).

Test Mode 4


1. http://cp.literature.agilent.com/litweb/pdf/5989-7528EN.pdf
2. http://citeseerx.ist.psu.edu/viewdoc/download?doi=

To be continued


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