DDR3 and Signal Integrity
DDR3 improves upon the speed over DDR2. While DDR2 works upto a maximum JEDEC supported frequency of 800 MBps, DDR3 can work upto 1600 Mbps. The Speed increase, however, does not lead to the linear increase in the throughput owing to the increase in the cache latency.
DDR3 leads to several design challenges in maintaining the Integrity of the Signal on the PCB. Its operating voltage has been reduced from 1.8V to 1.5V leading to 17% reduction in the voltage and c lose to 25% reduction in the power consumption.
Its partial refresh feature which is used to refresh only the active part of the DRAM while in sleep mode further improves the battery performance.
From the topology point of view DDR3 utilizes dynamic on-die termination (ODT), ZQ calibration, and a fly-topology all designed to improve signal integrity. In the On die termination, the termination resistors are placed on the chip itself rather than that on the PCB outside the chip. By Dynamic on die termination we mean that we can change the termination on the fly as required. The ZQ calibration command is used to calibrate the driver impedance and the termination resistance value which takes care of the process variation due to temperature, voltage or the board discontinuity.
The topology of the address and control lines in DDR3 chain from one DRAM to another, unlike DDR2 uses a T topology. This however, introduces skew between the signals.