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DDR Settings in Sabre Lite for i.MX6

September 16th, 2013

We were examining the memory configuration of the freescale i,MX6 Sabre lite board and found that some values of the configuration makes it work and other don't.

The main difference was due to locations 0x80c and 0x810 of the MXC_DCD_ITEM in the file board/freescale/mx6q_sabrelite_flash_header.S . The value that makes it work is

0x80c 0x001F001F
0x810 0x001F001F

And this one makes the board fail to boot.

0x80c 0x00440044
0x810 0x00440044

We figured out that the follwing lines ( at around line number 300) may make the optimal values for this board.

#MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
#MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
#MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
#MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)

#MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x00440044)
#MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x00440044)

MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x0023001B)
MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F0025)
MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x0026001E)
MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x00200027)

Most optimal values after taking into account trace delay of individual Byte lanes

We also notice the differences in the location 0x818 ( observed value 0x00022227). This difference is in Sabrelite and SabreSD. We will investigate and report more later.


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