Archive for October, 2015

PCB Via for High Speed Design

October 27th, 2015

The topic of PCB via and its capacitance with reference to the High Speed design was briefly discussed in the book Signal Integrity for PCB Designers, here . The topic requires a little more in depth analysis in 1 GHz and beyond range. Here are key points about via

1. The Via is predominantly capacitive. The top and the bottom pads of the via are main sources of the capacitance. Also the inner pads are electrically coupled with ground and power planes give additional capacitance. We should therefore try to minimize the size of the pad. It will require keeping the drill size to bare minimum. In most PCBs, the minimum drill size is of the order of 8 mils. Since the typical minimum trace width is 4 mils, the diameter of the pad is typically 16 mils at the minimum.

2. Enlarging the size of the antipad reduce the coupling of the pad and the drill with the ground layer and reduces the capacitance. For exact size of the antipad, a 3D simulation software should be used.

3. The drill length connecting the top and the bottom pad is predominantly inductive. This creates the inductive discontinuity. The length of this inductive discontinuity is typically 0.063 inch, which corresponds to 10.7 ps, assuming the speed of propagation in inner layer to be 170 ps per inch.

4. The inductive discontinuity starts playing role, when the rise time of the signal is less than 10x the electrical drill length of via. This rise time corresponds approximately to 107 ps. Whenever, time the rise time is less than about 100 ps, start considering the inductive discontinuity due to via. The lower the rise time, the more marked is the inductive discontinuity.

5. As a first order approximation, the via can be modeled as a pi circuit with two capacitor and one inductor as shown in following circuit.


The two capacitors correspond to the top and the bottom pads and the inductor correspond to the drill from top to the bottom.

6. As a first order the capacitance of the via can be given by the following formula.



εr = relative dielectric constant,
D1 = diameter of the via pad in inch,
D2 = diameter of the anti-pad in inch,
T = thickness of the PCB in inch,

7. According to the formula, increasing the Antipad size D2, and reducing the via diameter D1 reduces the via capacitance.

8. You can use the via capacitance calculator for a first order via capacitance calculator.

9. The above formula assumes that the inner ground layers are continuous and forms kind of a coaxial surface around the via drill. In that sense, it over estimates the via capacitance. In other words, it assumes presence of infinite number of ground planes. It also overestimates the effect if the anti pad. The formula also assumes that the size of the pads are same in the outer as well as the inner layers.

10. As a gross approximation, the via inductance can be estimated as


d = diameter of the drill hole in inch
h = thickness of the PCB ( or via length) in inch

11. The via inductance does not take into account any return path for the current. If there is a nearby via, the inductance of the loop will be substantially smaller.


Winter Sale of Signal Integrity for PCB Designer

October 12th, 2015

Signal Integrity for PCB Designers is now available for only $40 ( The price at amazon is $55).


Signal Integrity for PCB Designers 1st Ed by Vikas Shukla ISBN-13 978-0982136904


Parts used in Chromecast 2015 ( or Chromecast 2) - with prices

October 9th, 2015

Google recently upgraded its Chromecast and we now have faster dual core Marvell 88DE3006   Cortext A7 processor in the Chromecast 2 also being called Chromecast 2015. The wifi and bluetooth is now provided by Marvell's 88W8887, which also encompasses, NFC and FM receiver.  Google has been able to put together everything in a price of $35. Let us take a look at the price break up of the different components used .

S No Description Manufacturer Part No Cost
1 Wifi, Bluetooth, NFC and FM receiver Marvell 88W8887 $5.00
2 1500 Mini Plus dual-core ARM Cortex-A7 media processor Marvell 88DE3006 $14.00
3 2 GByte NAND Flash Memory Toshiba TC58NVG1S3HBAI6 $4.00
4 2 Gb ( 512 MBytes) DDR3L SDRAM Samsung K4B4G1646D-BY $5.00
5 Semiconductor DC-DC regulator Marvell MRVL 21AA3 521GDT $3.00
6 Other components / Connectors / Shield Heatsink Misc MISC $1.00
7 PCB Misc MISC $1.00
8 Manufacturing and Testing Misc MISC $1.00
9 Package, Cable, Power Supply Misc MISC $1.00
Total $35.00

We are, of course, assuming that google is not making any profit out of Chromecast. we do not expect the numbers to vary much from what we have discovered ( assuming the high volume). If you decrease the price of one you will have to increase it somewhere else.

Changes from Chromecast 1

The first major change is the upgrade in from the Azurewave AW-NH387 that used the Marvell 88W8787 chip to newer Marvell 88W8887 chip. The 88W8887 provides support for 802.11ac ( for 5 MHz band for faster data rate) absent from Chromecast 1. Th Marvell chip also has support for NFC and upgrades bluetooth to 4.0 from 3.0.

Second major change is the SoC itself upgraded from Marvell DE3005-A1. This should make navgation a bit smoother, but frankly, for the kind of the application this product has been designed, you do not need much of a processing power.

The RAM and the Flash chips have been changed but the densities are same ( 512 MB RAM and 2 Giga Byte Flash).

By Vikas Shukla

- I started working on a new site CPU Compare . I will be focusing less on this site for a while.


Gigabit Ethernet validation

October 9th, 2015

Once you have taken care of the high speed routing rules for Gigabit Ethernet , it is time for the electrical validation test of the Gigabit Ethernet. We will cover the steps involved in the electrical validation of the Gigabit Ethernet. The freescale i.mx6 board with KSZ9021RN chip will be used as an example ( to show test mode settings), but it should be similar for other test scenario.

The Gigabit standard defines of four test modes for testing. These modes can be set by writing to bits 13 to 15 of Control register 9.

Setting Test mode in Freescale i.MX6

The test mode for the Phy chip KSZ9021RN can be set by stopping the boot of the processor at u-boot. Following mii commands can be used to read or write the control registers.

mii device //set current device
mii info //display MII PHY info
mii read //read MII PHY register
mii write //write MII PHY register

Note that there is a bug in freescale i.MX6 uboot source code that prevents the execution of this code.

Test Mode 1

In test mode 1, all four pairs, transmit signals in a predefined manner. This pattern in captured in the following figure.


The point A in the signal correspond to +2 level. In the test signal fist a +2 level is sent and is followed by 127 duration of 0 Level, and is followed by a -2 Signal, represented by B. Then again 127 duration of 0 and then +1 level ( shown as C), then again 127 0s followed by -1 Level ( shown by D).

We then measure the levels at A, B, C and D. The measurement should conform to the following specifications.

1. The absolute values of the peak of the waveform at points A and B shall fall within the range of 0.67 V to 0.82V.
2. The absolute values of the peak of the waveform at points A and B shall differ
by less than 1%.
3. The absolute values of the peak of the waveform at points C and D shall differ
by less than 2% from 0.5 times the average of the absolute values of the peaks
of the waveform at points A and B

The test fixture is used to terminate the Transmitter pairs. It consists of terminating the transmitter pair with two 50 Ohm resistors with center of these two resistors connected to a signal generator. The signal generator transmits a
sine wave with specified frequency and amplitude (1.4 V peak to peak @ 31.25 MHz, in the above case). The purpose of the disturbing signal is to simulate the presence of a remote transmitter.

A high impedance differential probe is used for measurement and a filter is placed between the test point and the probe point. A typical test fixture is shown here.

Template Test

The waveforms at Points A, B, C, D, F, and H have to fit in defined shape (templates). This is measure after making the signal go through a 2-MHz high-pass filter. It is also normalized according to rules described in sub-clause of IEEE Standard 802.3-005. The High speed filter and the normalization step can be done in some of the digitizing oscilloscopes that support these functions.

A typical normalized wavform along with the template is shown in figure below.


Droop Test

Droop test is performed on the long strings of the "+2" and "–2" symbols. Referring the first figure above the voltage droop is measured from point F (minimum point at the start of "–2" symbol string) to point G (500 ns after point F) as well as from point H (maximum point of the waveform as indicated in Figure 3) to J (500 ns after point H).

The template test and the Droop tests are performed in test mode 1.

Test Mode 2

The test signal in mode 2 consist of alternating "+2" and "–2" symbols and is timed to a 125 MHz timing clock called the TX_TCLK. The test mode 2 used device's own 125 MHz Transmit clock..

Test Mode 3

Test mode 3 is same as test mode 3, except that it uses a recovered clock from the data transmitted by a Link partner in Master mode.

Jitter Test

The Clock signal in test mode 2 and test mode 3 is analyzed for jitter measurement. It should be within the specified specification. ( To be updated).

Test Mode 4



To be continued


AW-NH387 for low cost wifi and bluetooth on i.MX6

October 5th, 2015

I had earlier published a post on the wifi and bluetooth options for freescale i.MX6. I had included the USB option, Broadcom and TI based modules. None of these were ultra low cost.

Today I started looking at the parts used in Google Chromecast, and my special interest was the wifi module used in it. Since the Chromecast is very inexpensive ( $35), and it does support wifi and bluetooth, it was bound to use low cost option. The Chromecast teardown revealed that the chip used for the Wifi and Bluetooth is Azurewave AW-NH387. This part is available at $5.2800 in quantity of 500 from Arrow.

AW-NH387 uses Marvell 88W8787 chipset. The block diagram shows the inner details of AW-NH387.


The AW-NH387 is also sold at Embedded Works and has its own part number as EW7830CB.

Attempting to check if this low cost Wifi is also supported on i.MX6, led to compulab module that does not mention the Azure wave but does lists out the Marvell 88W8787 as the chipset supported for Wifi.

The features of the 88W8787 includes

1. Wifi 802.11a/g/b but NOT 802.11ac. The 802.11ac has the potential to provide faster data rate using 5 GHz band that uses more bandwidth.

2. Bluetooth 3.0 + High Speed (HS) . This is also compliant with Bluetooth 2.1 + EDR.

3. FM Receiver

Marvell has since then upgraded 88W8787 to 88W8887 which now supports 802.11ac. It also supports BT 4.0. The newer 88W8887 aslo has integrated NFC.

Google has used the 88W8887 in place of Azure Wave module, in the newer 2015 Chromecast.


Skylake Vs Haswell Desktop processors

October 4th, 2015

To make the comparison of the Skylake and Haswell, I made a list of the i7 and i5 series processors in both line ups that had same or similar clock frequencies and number of cores/hyperthreads. We then plan to compare the benchmarks of these processors to see how much is Skylake better just by architectural improvements. So here is the list

Family Processor Cores/Threads Based Clock Turbo Clock Cache
Skylake i7-6700K 4/8 4.0 GHz 4.4 GHz 8 MB
Haswell i7-4790K 4/8 4.0 GHz 4.2 GHz 8 MB
Skylake i7-6700 4/8 3.4 GHz 4.0 GHz 8 MB
Haswell i7-4790 4/8 3.6 GHz 4.0 GHz 8 MB
Skylake i5-6600 4/8 3.3 GHz 3.9 GHz 6 MB
Haswell i5-4670 4/8 3.4 GHz 3.9 GHz 6 MB
Skylake i5-6500 4/8 3.2 GHz 3.6 GHz 6 MB
Haswell i5-4570 4/8 3.2 GHz 3.6 GHz 6 MB
Skylake i5-6400 4/8 2.7 GHz 3.3 GHz 6 MB
Haswell i5-4430 4/8 3.0 GHz 3.2 GHz 6 MB

Skylake i5-6500 vs Haswell i5-4570

While all of the above pairs listed in the table match very closely in terms of base and turbo clock frequency the two that stand out very clearly are the Skylake i5-6500 and the Haswell i5-4700. The have exactly same base clock frequency at 3.2 GHz and turbo clock frequency of 3.6 GHz. The two processors also have the same amount of the Cache memory at 6 GB. They do differ in terms of the memory controller which has been upgraded to DDR4 for the Skylake.

The passmark scores of the Skylake i5-6500 stands at 7122 and that of the Haswell i5-4570 at 7020 giving Skylake an advantage of 1.45%.

The Skylake does make an improvement in terms of the power envelope where the TDP rating has been reduced from 84 Watts to 65 Watts and that is substantial. But as far as the end users are concerned, the 1.45 % improvement in a period of 2 year is something to be disappointed about. It may be time Intel stops yearly upgrade of processors and give itself some more time to bring some real improvement. That will also work better for its own financial by not requiring to upgrade its fab as often.The users benefit by not worrying to upgrade to soon and too often.