SOC designs require standard bus architecture for IP cores to communicate There are other interconnection schemes like AMBA and CoreConnect but wishbone has several advantages over them as designers can select IP cores from the site and connect it to wishbone according to design specifications secondly it contains all features of AMBA and CoreConnect
Wishbone SOC interconnection architecture is a flexible design methodology for design with semiconductor IP cores.It is a standard interconnection scheme and common interface specification to design structured design methodologies on large projects.Different IP cores developed independently can be tied together and can be tested by standard IP core interfaces.Many reusable designs are available are compatible with WISHBONE standard.Designers has to collect IP cores and integrate it into design to complete SOC design.All these cores are free of cost and reusable.Hence it helps in making low cost,portable,reusable design.
To create portable interface that supports both ASIC and FPGA design that is independent of semiconductor technology and of logic signalling level.
To provide standard interface that can be written using languages such as VERILOG and VHDL.
Provides simple compact logical IP core hardware interface that require few logic gates
Supports single clock cycle data transfer
It provides variety of bus transfer cycle cycles in which data transaction is independent of application based IP cores
Provides different types of interconnection architecture
WISHBONE INTERCONNECTION SCHEME
The figure given below shows wishbone interconnection scheme
Here master initiates the communication by providing address and control signals to slave and then slave respond to master with specified address range.The INTERCON system provides interface between master and slave for data transfer between them.The SYSCON provides wishbone clock and reset signals for proper functioning of system.Fig1 shown above clearly describes the process.Wishbone INTERCON are designed to operate over infinite frequency range and can be described using hardware languages like VERILOG or VHDL
Wishbone interface specification is used to specify signalling method used by master,slave and syscon module.It also provides a way to create documentation wishbone compatible IP cores which can be reused.Wishbone compatible IP cores must be provided with Wishbone datasheet.Wishbone datasheet contains the below information
The revision level of wishbone after which it is designed
If IP designed is Master or Slave IP core
Signal name used in the design must be specified.If any signal name is different from defined specification then it must have a cross reference to original signal specification
How the master reacts to error and retry signal and how slave generates error and retry signal
The design supporting tag signal must specify TAG TYPE and operation of tag
The port size must be 8bit,16bit,32bit or 64bit
Data transfer ordering such as LITTLE ENDIAN and BIG ENDIAN must be specified
Any constraint on the clock signal must be specified in terms of clock frequency
WISHBONE INTERFACE SIGNALS
Interface signals are divided into three parts master signals,slave signals and signals common to both master and slave
Signals must allow master and slave to use variable interconnection
Signals must support all basic types of bus cycle
Handshaking mechanism must be used for either master or participating slave to adjust data transfer
Every interface must support acknowledgment signal and retry and error signals are optional
Address and data bus width can be 8bit,16bit,32bit or 64bit
All signals must be either input or output.If bidirectional then target device should support it
WISHBONE BUS CYCLE
Three types of bus cycle is supported by wishbone interface
• Single read write
• Block read write
• Read modify write(RMW)
All bus cycles follows the handshaking protocol for the transfer of data between master and slave.
Handshaking protocol is used in transfer of data between master and slave.The transfer is divided into four parts
• Operation requested
• Slave ready
• Operation over
• Ready for new operation
Here the master asserts strobe indicating data is ready to be transferred,strobe remains asserted until slave asserts acknowledge signal indicating that it is ready to participate in data transfer.At every rising edge of clock terminating acknowledge signal is sampled and if asserted then strobe signal is negated showing the completion of operation.In response slave negates its acknowledge signal indicating it is ready for new operation.