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Archive for May, 2015

Power Operator ** in Verilog ( Especially 2 to Power N)

May 24th, 2015

The 2001 edition of Verilog introduced power operator using **.  The x**y, for example mean x to the power of y.  The most common us of power operator will be 2 to the power N which will also be easiest to understand from synthesis perspective. This code snippet, for example compares if all bits of an N bit register are one.


...

parameter N = 4;

...

....

assign clock_out_tick   =  (reg_value == 2**N-1)  ?  l'bl  :  l'b0;

Let us say N is 4. In that case 2**N -1 will have a value of 15 or 4'b1111. This is part of a code that gives a "clock tick" or a  1 signal for 1 clock period when counter reaches its maximum value.

If  N were not a parameter we could possibly have written this code


assign clock_out   =  (reg_value == 4'b1111)  ?  l'bl  :  l'b0;

You will also find its usage in localparam declaration often as in

localparam N;
localparam ALL_BITS_1       = 2 ** N -1;

Anytime you see 2**N-1 mentally assumes that it is equivalent to making all N bits 1.

In general, the operands of the power operators can take values other than 2 and N mentioned here. For example.

4**3 evaluates to 4*4*4
3**0 evaluates to 1

Some special cases
Hopefully you do not come across these - but just in case - if you raise a negative power to 0, it will become undecided.

0 **(-1) evaluates to 1/0 or 'x

Difference with C

In the power ^ is used for power operation. So 2^3 will mean 23. In verilog the ^ was taken up for Exclusive OR and hence the FORTRAN style ** was used for power operator. The Section 11.4.3 of Verilog reference manual describes the power operator.

More verilog tutorial here

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Verilog Clock Divide by 3 - Synthesis Issue and others

May 22nd, 2015

A clock divide by 3 has to work in one way or the other on the positive as well as the negative edge of the clock. We started working at the following verilog code to implement the divide by 3

module clk_div3(clk,reset, clk_out);

input clk;
input reset;
output clk_out;

reg [1:0] r_reg;
wire [1:0] r_nxt;
reg clk_track;

always @(posedge clk,negedge clk)

begin
  if (reset)
     begin
        r_reg <= 2'b0;
	clk_track <= 1'b0;
     end

  else if (r_nxt == 2'b11)
 	   begin
	     r_reg <= 0;
	     clk_track <= ~clk_track;
	   end

  else
      r_reg <= r_nxt;
end

 assign r_nxt = r_reg+2'b01;
 assign clk_out = clk_track;
endmodule

The code works well as far as compilation is concerned. However, when we started implementing it in Spartan 3,
it turns out that Xilinx shows following error in the Synthesis.

ERROR:Xst:899 - "comparator.v" line 37: The logic for <r_reg> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "comparator.v" line 38: The logic for <clk_track> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

It turns out that the Spartan 3 in particular and Spartan 3 in particular does not support flip flops that work on positive
as well as negative edges.

For example if we change the line

always @(posedge clk,negedge clk)

to

always @(posedge clk)

The synthesis is proceed without error. However, we have a divide by 6 and not divide by 3 circuit as you can see from the following screen shot capture on a Xilinx evaluation board.

clk_div_by6

So what is the solution ?

One approach is to have two separate always block - each working on a positive and a negative edge of clock and then to combine the two in some way.

To understand it, consider that we keep two counters, one that counts the number of  positive rising edge and other that counts negative rising edge. The counter counts 0,1, 2 and then 0  as in the following diagram.

divby3_counter

We can make use of this counter to generate a positive clock for three half cycles and negative clock for next three half clock cycles.  Look carefully at the diagram and look for the periods where at least one of the counters is 2. The assign high to clock_out for these periods. And then assign 0 to rest of the time periods.  If you can understand this, the following code should be easy to understand.


module clk_div3(clk,reset, clk_out);

input clk;
input reset;
output clk_out;

reg [1:0] pos_count, neg_count;
wire [1:0] r_nxt;

always @(posedge clk)
if (reset)
pos_count <=0;
else if (pos_count ==2) pos_count <= 0;
else pos_count<= pos_count +1;

always @(negedge clk)
if (reset)
neg_count <=0;
else  if (neg_count ==2) neg_count <= 0;
else neg_count<= neg_count +1;

assign clk_out = ((pos_count == 2) | (neg_count == 2));
endmodule

Notice the statement


assign clk_out = ((pos_count == 2) | (neg_count == 2));

This basically implements the logic that we observed. Also notice that we could replace the above with


assign clk_out = ((pos_count == 1) | (neg_count == 1));

or with


assign clk_out = ((pos_count == 0) | (neg_count == 0));

Here is the output waveform for this code. This was synthesized and verified on Spartan 3.

divby3_syntethised

The output clock in this scheme may have glitches at the crossings produced by the combinational logic.

FPGA's generally have dedicated PLL and clock circuit that provide low jitter clocks. They have generally capability to multiply by 2 or divide by 1.5, 2, 3, 4.5 etc. These should be used, especially for higher clock frequencies. The idea presented here can be used for slower clocks and for division of a clock by an odd number.

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Verilog Initial block synthesis

May 4th, 2015

In Verilog, Initial blocks are used in test benches. There may be one or more than one initial block all running simultaneously right at the beginning.

Can initial block be also used in synthesis. For example, you may be tempted to write the code as follows

module dff_not_synthesizable(clkin,q,d);
input clkin,d;
output q;
reg q;

initial  // Not synthesizable

begin
 q <= 0;
end 

always @ (posedge clkin)
begin
 q <= d;
end 

endmodule

We are trying to make sure that initially the output is 0 using the initial statement

begin
q <= 0; end However, the code will not synthesize. We should be using a reset input instead, to make make initial value of the output of the D flip flop low at the time of reset. Initial blocks are non synthesizable blocks. Why the hell then is it included in Verilog ? To confuse the students ? Well, generating synthesizable code is not the only purpose of Verilog. A lot of effort goes on in verifying the code that is synthesizable. And hence we need a lot of other constructs and initial block is one such construct. The $display, $monitor etc are other such constructs that will not synthesize, but will help in testing the code.

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