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Archive for March, 2009

“Signal Integrity for PCB Designers” - A critique

March 30th, 2009

Harry,

I value your time and feedback especially your observation about the copper pour. For Tom and Bob section, I actually thought that some people may find it interesting. But I do understand that it dilutes the gravity of the subject.

The book did not go through an independent review, editing and proofreading before print. Fortunately, only few prints have been out ( only 25 or so). Page numbers issue is obviously first candidate that will be fixed as also typographical errors in the next print.

The book definitely deserved more time and attention than I had given before sending it to print. The fonts are much larger which I had noticed but I was too lazy to fix it. Perhaps in next edition. Perhaps will include topics of via fencing, and via peppering as also some more topics that I had in mind but required simulation and experimentation.

I once again appreciate your time and feedback and critical analysis. Something that was missing from the feedback I received from friends.

Best Regards,

Vikas Shukla

Harry Selfridge’s observation about the book “Signal Integrity for PCB Designers” by Vikas Shukla

Mr. Sukla Vikas,

I received the book on Saturday, 28 March 2009. The envelope was
torn in several places and had been taped by the postal service to
hold it together. The book itself was in good condition, except for
a small tear on the bottom edge of the rear cover.

After only two days of reading, it is painfully apparent that very
little proofreading and editing was done before printing. The index
requires a bit of mental math to utilize - all of the page numbers in
the index are off by +13. There are large numbers of grammatical and
typographical errors throughout the book that detract from
reading. Additionally, the three different fonts for epsilon
(dielectric constant) used in the book may be confusing to
non-engineer PCB layout designers. Finally, it is not a major issue
but different thickness values are given for 1oz copper in various
places throughout the book - 1.35 and 1.37 are two I’ve noticed thus far.

Some topics are glossed over to the extent that a novice could get
the wrong impression. For example, the remark in the section
regarding board warping that states “…fill up the remaining are
(sic) with copper, even if they are not connected to a net.” A
blanket statement such as that ignores the potential capacitive
coupling between objects on an adjacent signal layer, or the resonant
cavities that could be formed by randomly inserting patches of dead copper.

I like your selection and presentation of topics; however, I dislike
the “Tom and Bob” dialogs. It is apparent you are trying to make dry
subjects more informal and appealing; however, a similar result could
be achieved in a less condescending way with bold face, or
italicized, questions followed by discussion. Perhaps younger people
will appreciate your technique, but it annoys this old engineer.

I will pass your book to PCB designers, but only with a note of
warning to be aware of the index problems, grammatical mistakes, and
typos. I will also caution them not to ascribe absolute accuracy to
issues like dead copper. Additionally, I will include a handout on
via fencing, and via “peppering” - two overused and misunderstood PCB
layout techniques I wish you had included in your book.

Regards,
Harry Selfridge
VP Engineering
Encore Engineering Services and Products

Uncategorized

Review of Book - “Signal Integrity for PCB Designers” by Vikas Shukla

March 30th, 2009

 Signal Integrity for PCB Designers by Vikas Shukla 

I received the book this past weekend.  I browsed through the material,
and have read the preface and started chapter one.  I'm looking forward
to reading the entire book and   applying the techniques as well.  I
think this book will make a great addition to my PCB library.
Thanks,
Richard 

richard.upton@ngc.com

Signal Integrity ,

Inductor and Calculation of Inductance

March 15th, 2009

I received these in my emails from si-list during July 2003.

Hello experts:

For a microstrip, we know the magnetic field distribution(for example, Fig. 2.3 Stephen Hall’s book) and current density distribution(Fig. 4.5 same book). Given these, how would you obtain the inductance distribution?

Thanks in advance,
Sainath

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Hello Sainath,

inductance is the proportional factor between the current and the magnetic flux. So far Your idea is ok. But calculating magnetic flux from magnetic field requires an integration across a closed surface surrounding the conductor carrying the current. So - as You see - You will not get a inductance distribution over conductor length but only an integral value for the conductor enclosed in the chosen sphere.

Sorry,
Thomas

Thomas,

Thank you. I agree, you get one value of inductance for one integration.  If you repeat this for a number of ‘concentric spheres’, you will get a  number of inductances- ranging from minimum to maximum. Does that make sense?

Sainath

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Sainath,

As Thomas pointed out, inductance is the ratio of magnetic flux to current in the conductor. Magnetic flux is the integral of B dot dA, or the magnetic field [dot product] the surface you are integrating over. The “dot product” is the same as multiplying the B-field by the area by the cosine of the angle between the B-vector and the normal to the area. So if the B-vector is perpendicular to the area surface, then the B-vector is parallel to the unit normal vector of the area surface, cosine of this zero degree angle is 1, and you simply multiply B*area. Here’s an example to illustrate.

You have a rectangular metal trace over a ground plane, length in the z-direction, height in the y, width in the x. Stretch a rectangle in the yz plane between the trace and the ground plane. Make it any length (smaller if you are simulating with EM tool). If we assume perfect conductors (ie no internal-conductor magnetic fields), then all of the magnetic field associated with that signal trace will pass through this rectangle. It is
kind of like a net. Magnetic field lines always have to end up in the same place they started, completing the circle. Also, in this configuration, all your field lines are perpendicular to the integrating rectangle. So
inductance is flux/I = B*A/I. In this case, you will actually have inductance per unit length because your net had a specific z-length.

If you were to put your integrating surface on the other side of the trace, extending up from the top of the trace, you theoretically would have to make the area of the surface extend to infinity to “catch” all the field lines. By placing it between the signal line and the return path, you capture all the field lines. So you have one number for inductance if you account for all the B field lines. An inductance “distribution” would indicate that you are not catching all the magnetic field lines with your integrating surface.

This might open up a talk about internal inductance, when you have magnetic field lines (ie current) INSIDE the conductors. As frequency increases, the current crowds to the surface, and the internal inductance diminishes. But at lower or intermediate frequencies, this internal inductance can be a contributing factor. For PCB’s, this is typically in the low MHz range. But for square conductors on silicon, measuring a few microns wide and a few microns high, the internal inductance might have to be considered up to
several GHz. Does this affect you? Do you electrical models consider this effect? How about internal inductance of the ground plane? Interesting stuff here.

Salud,
Andy Byers

Andy,

Thanks. I appreciate the extra effort to explain detail of integration. In short, you’ve explained the current loop formed by a signal path on trace and signal return path beneath the trace and on the ground plane.
Such a return path, with its minimum loop area, is widely known to provide the path of “least” inductance for high-frequency currents(for example, Black Magic book). If inductance is thought of as one number,
what does “least inductance” refer to? Which is the path of “most” inductance for the microstrip? No doubt, I’m missing somethig.

Sainath

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Hello Sainath,

Clearing up some terminology here.

“Least inductance” refers to the path that the current will travel because will never choose an alternate path of “most inductance”. BUT you can have a different design in which the “path of least inductance” is longer. For example a two wire line with no ground plane where the wires are extremely far apart. Huge loop, huge inductance. But still the smallest loop for that system. For a microstrip, a path of More Inductance would be if there were a gap in the ground plane under the microstrip line. The current would be forced to diverge around the gap. This path would be more inductive than a solid ground plane, but the current would still be following the path of least inductance for that particular case.

The main challenge in most systems I’ve dealt with is making sure that return current paths have the least inductance possible. The simplest way to do this is go differential. Then you carry your virtual ground with you everywhere. If single ended, then be very conscious about where the return currents flow and try to provide a short path. Plenty of threads on this list about that.

Not sure if this clears up your last question, hope it helps though.

- Andy

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Hi Andy,

Thanks again. I get the themes that inductance is a one number affair  and current returns through the least inductance path. Is there a  contradiction in these themes?

Let me borrow the following from your previous mail.

“If you were to put your integrating surface on the other side of the trace, extending up from the top of the trace, you theoretically would have to make the area of the surface extend to infinity to “catch” all
the field lines.”

For this case, is the inductance of the microstrip going to be infinity(because of infinite surface)? or any other value? remains same as what it was for the integrating surface below the trace?

Sainath

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As someone previously stated, inductance is defined as the ratio of the magnetic field to the current. BUT both of those are vector quantities, not single numbers. And there is a different quantity for each point in a field. So “single values” for inductance are obviously simplifications. My interpretation of “the path of least inductance” would be the set of connected points for which the value of inductance is least.

Art Porter

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Inductance is the ratio of magetic flux (not field) to current. Flux is not a vector, it is a scalar. So is the magnitude of the current in a wire (closed integral of H dot dl). So you will get single inductance number for
a specific interconnect cross section.

See pg. 81-83 of “Fields and Waves in Communications Electronics (3rd ed)”, Ramo,Whinnery,and Van Duzer.

As you progress down the interconnect, the current will want to flow wherever this inductance in the smallest. The path that the current follows will be this path of “least inductance”.

Happy Weekend!

Andy

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Andy,

Yes, the inductance value should remain the same for both cases. Also, we are capturing all the magnetic flux lines in both cases.

Now comes the real question. When you capture all the flux lines, is the inductance going to be maximum? or minimum?

Sainath

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Sainath,

First of all, with your surface, either above the microstrip or below, you are capturing magnetic field lines, not “flux lines”. You integrate these field lines over the area of the surface to produce a scalar number which is your magnetic flux. A lot of times people get Flux and Field confused. Flux is a scalar number, while field is a vector.
So, like you say, if you capture all the field lines on your surface, you should calculate the true flux and therefore the correct inductance. Calling it a “maximum” or “minimum” does not really fit here. If you were to use a surface where you did not account for all the field lines, the inductance you calculate would indeed be smaller than the correct value. But it would be wrong. I guess you could say that “maximum” inductance calculation is correct, and “minimum” inductance calculation would be zero (you capture
none of the field lines).

Any 2D cross section of an interconnect system should have one correct inductance value. As you move along in the 3D direction of propagation, the 2D cross sections will change and your inductance at that point might change too. Once again this is assuming no internal inductance and a single mode.
With internal inductance, your total inductance becomes frequency dependent. The Ramo, Whinnery, Van Duzer book points this out as well.

Andy
_______________________________________________________________________________

Andy,

Calling it a “maximum” or “minimum” does not really fit here.

C’mon! Let me explain why calling it a “maximum” or “minimum” does  really fit here.

1) No other integration surface (other than the two we considered)can give a more inductance value. Right? So, obviously it is the maximum inductance value.

2) Conventional notion is that return current takes the path of minimum inductance and hence flows directly under the trace on the ground plane. Contrary to this notion, through this thread, we observed that such path provides maximum inductance.

Unless I’m missing something big time…

In conclusion, the return current, when it flows directly under the trace on the ground plane, is in fact taking the path of maximum inductance. In other words, the path directly under the trace on the ground plane is not the path of minimum inductance.

Sainath
_______________________________________________________________________________________

Wow - This is getting interesting. Heres my take on it. One can say that inductance is proportional to
field lines. SO more field lines  (or flux) the higher the inductance. In thace case of two parallel wires, Flemings RHR shows that the field BETWEEN the lines in enhanced - maybe  leadind one to think maximum inductance. However the fields on the *outside* of the wires actually cancels leading to
a reduction in overall inductance of the loop.

Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
_____________________________________________________________________

Andy,

I disagree with your correction(about integrating magnetic flux lines). Please do a simple dimensional check.

Yes, there is this correct inductance value which we get in the limiting  case when we capture all the flux. This is also the maximum inductance. Lower inductance values are possible depending on the chosen surface and the minimum can go as low as zero, like you said. So, there is a distribution ranging from zero to the correct value. I believe the significance of this and its SI application opens up new directions…

For SI application involving return current paths, I wonder how the idea of minimum(zero) inductance path stuck around so long.

Sainath

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Sainath,

The integral (maximum or minimal) depends on the loop of the surface edge, not the surface itself. Given a fixed loop, the integral will not vary on various surface. Its principle comes from the physics law that tells us the integral on a closed surface is always ZERO.

Fred
_______________________________________________________________

Fred,

We’ve been talking about magnetic flux which is the surface integral of the normal component of flux density vector B. Right? Given that, please check your statements.

Sainath
__________________________________________________________________

Sainath,

You are getting confused between the calculation of the inductance for a given current distribution and the variation of inductance caused by a variation in current distribution.

When you are calculating the inductance value for a given current distribution, you must integrate the normal of the B field over a surface area which captures ALL of the field lines surrounding (external
inductance) and within the current distribution (internal inductance). This is not the maximum inductance or the path of maximum inductance, it is simply the correct inductance.  Any calculation which uses a surface
area which fails to have all of the field lines passing through it is wrong.  Inductance (not partial inductance) is defined as the ratio of the amount of magnetic flux coupled through and created by a given
closed path current distribution to that current distribution.  The irrelevant fact that performing the calculation while ignoring some of the field lines happens to give a lesser inductance value does not make
the correct calculation the maximum inductance value.  By your logic, if I could find a different but equally wrong way of calculating the inductance and it happened to come out larger than the correct calculation, then the correct calculation should henceforth be known as the minimum inductance value.

If I were to integrate the electric field lines passing out of a closed surface and decided to ignore part of the surface, I would get a value for the charge within that surface which was smaller than the correct
value.  Should I then refer to the charge within that surface as the maximum charge value?

The path of maximum inductance within the conductor would be the current distribution which maximizes the open surface area required to couple all of the B field. The path of minimum inductance within the conductor would be the current distribution which minimizes the open surface area required to couple all of the B field.  The change in inductance is linked to the variation in loop size caused by the variation in current
distribution.

Additionally, as has been stated on this thread, the current will distribute itself on the path of minimum impedance or referring to the principle of least action, the path of least energy; depending on frequency this is not necessarily the path of minimum inductance.

Thanks,

Michael Smith
iZ Technology Corp.
________________________________________________________

Michael Smith,

>By your logic, if  I could find a different but equally wrong way of calculating the inductance and it happened to come out larger than the correct >calculation, then the correct calculation should henceforth be known  as the minimum inductance value.

- That is what I need. Please give me a way to find an inductance value
that is larger than the correct value.

>The path of maximum inductance within the conductor would be the current distribution which maximizes the open surface area required to couple all of the B field. The path of minimum inductance within the
conductor would be the current distribution which minimizes the open surface  area equired to couple all of the B field.  The change in inductance is linked to the variation in loop size caused by the variation in current distribution.

- I don’t quite follow this technical language. Is there a reference you could suggest me on this?

>Additionally, as has been stated on this thread, the current will distribute itself on the path of minimum impedance or referring to the principle of least action, the path of least energy; depending on frequency this is not necessarily the path of minimum inductance.

- We all seem to agree that high-frequency currents need not necessarily
follow the path of minimum inductance.

Sainath

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From: “john lipsius”

To all pursuers of the maximum/minimum false dichotomy and the “path of maximum annoyance”     :-)

Any further contributions to this thread that adhere to that confusion will, it seems, just confuse novices that subscribe to this list.  Any further help from the experts is, unfortunately, wasted I believe.

Please pick up a physics or microwave text to get it straight and look at the illustrations.   In short, it’s necessary to dot-product one’s interest with a little homework, whereupon the path of maximum edification shall reveal itself in all its glory and thence one shall go forth in peace and confidence.

A review of andrew’s and michael’s replies on this thread should suffice, below.

Basically, claiming there’s an inductance “distribution” is confusing these two:

1. a mathematical definition of flux that relies on an abstract  surface chosen by you

2. the flux itself, which is constant for constant current, frequency,  material and geometry.

-enough said

________________________________________________________________

Those of you interested in magnetic field theory may find Sainath’s questions about the integration of magnetic flux a fascinating subject; others may find this a good time to step out for a cup of tea…

Dear Sainath,

The mysteries of magnetic-field integration are indeed sometimes difficult to comprehend. In answer to your question about the surface of integration, the best mental image for this appears in the famous work by James Clerk Maxwell, “A Treatise on Electricity and Magnetism”. The first volume of this work (Electricity) is available on www.amazon.com as a modern reprint of an old Dover version, circa 1954. I read
a copy of the work in preparation for writing my latest book, “High-Speed Signal Propagation”, and found it most enlightening.

From the preface of Maxwell’s book, here is the key idea that renders sensible this whole business of integration of magnetic field intensity over a surface: “Faraday, in his mind’s eye, saw lines of force traversing all space”.

It’s the “lines of force” concept that makes everything work. What you need to know about Faraday’s “lines of force” idea, in the context of your problem having to do with evaluating the inductance of your trace, is that magnetic lines of force form continuous loops having no beginning and no end. The total number of lines extant is a measure of the total magnetic flux produced by a magnetized structure.

Of course you can re-normalize any magnetic field picture to produce a different number of lines by declaring each line to represent a different quantity of flux, for example 1/10th the original amount would produce 10x the number of lines, etc. Presumably you have scaled the flux represented in your (mental) magnetic field picture in such a way as to produce a manageable number of lines that is at once enough
to represent accurately the pattern of field intensity and also not too many to clutter the image. Keep in mind, however, that regardless of the number of lines, there are a finite number of them and each is a continuous entity forming a complete, unbroken loop.

In Maxwell’s view, integrating the magnetic flux passing through a surface is simply a matter of simply COUNTING how many lines pass through it.

For example, consider a closed surface (a sphere) in space. Any particular line that enters the ball must, since it cannot end within the sphere, exit at some other point. Therefore, when counting the number of lines penetrating the surface, since each line must both enter (a positive count) and also exit (a negative count), the sum of entrances and exits penetrating the sphere must be zero. From this simple idea Maxwell derives the idea that the integral of flux over any closed surface (of any shape) must be zero.

[Mathematical aside: you may be familiar with certain complications having to do with the integration of field vectors penetrating a surface whereby you have to dot product the field intensity direction vector with a vector normal to the surface--these difficulties dissappear when you simply "count lines", which is the beauty of Faraday's brilliant intuitive approach. When the surface is tilted so that the lines intersect the surface at an oblique angle, the number of lines penetrating each square area of surface is naturally reduced. This reduction is precisely accounted for, in multidimensional vector calculus, by the dot product.]

Now let’s apply the line-counting analogy to your trace-inductance problem. Imagine a certain finite number of magnetic lines of force wrapped around your trace. [I'll assume the reference plane is infinite in the x-y
directions. The plane is located at z=0, and the trace is at z=1. Since the plane is infinite, no lines of force exist below z=0.]

Assume I hook up my inductance meter to one end of the trace. Connect the other end of the trace to the reference plane. Now stretch an imaginary “soap bubble” in the region between the trace and the reference plane. Beginning at my end of the trace the edges of the bubble touch the trace all along its length, following along at the end down to the reference plane, returning along the plane to the source. For completeness, let’s also consider how at the source the edges of the bubble also must track along the ground lead of my inductance meter up to the instrument and then back down the signal lead of the instrument to the beginning of the trace. We’ll assume the meter is really tiny compared to the size of the trace so we don’t have to worry too much about the shape of the source end of the bubble (this is a serious real-life complication in the measurement of tiny inductances).

Next step: apply 1-amp of current to the trace, and count the number of field lines penetrating the soap bubble. Since the bubble is an “open” shape (i.e., it is bounded at the edges in such a way that it does not enclose any space), you will record some non-zero amount of flux penetrating the bubble. NOW comes the really cute part of this mental experiment. I want you to blow on the bubble, stretching it. It’s still anchored at the edges, but no longer a flat sheet. The remarkable thing that happens is that the number of magnetic field lines penetrating the bubble does not change. It doesn’t matter how you stretch or modify the shape of the bubble, or how far you blow it out of position, as long as you don’t change where the bubble is anchored
around the edges, you haven’t changed the number of lines penetrating it. That property (of the total flux  not changing regardless of the exact shape of the surface of integration used) is essential to understanding how to calculate inductance.

To prove that distorting the bubble doesn’t change the total flux, Maxwell imagines two surfaces, A and B, both anchored to the trace and plane just like your soap bubble. When connected together, these two surfaces A and B form a single closed surface. Therefore, using our earlier reasoning about the sphere, the total number of lines penetrating the combined object A+B (that is, coming into A and leaving through B) must equal zero–from which you may correctly deduce that when measured separately the total flux passing through A must precisely equal the total flux passing through B.

In a minute I’m going to directly address your question about making “the area of the surface extend to infinity to catch all the field lines”, but first I need to go over one more detail. That detail has to do with how an 2-dimensional surface with infinite extent acts kinds of like a closed surface, in that it partitiions space into two regions. Instead of the regions being “inside” and “outside” as they are for an ordinary closed surface, the regions are “this side” and the “other side”, but the partition exists just the same. I bring this up because the partition idea helps you see why the total flux penetrating any infinite plane must equal zero. Just like with the sphere, any line of flux that passes through the infinite sheet to the other side (a
positive count) must eventually make its way back (a negative count), making the total number of crossings equal zero. I’m now going to apply this idea (finally) to your problem.

I want you to turn your mental picture so you are looking at the side of the trace (a broadside view of your soap bubble). Color the bubble pink. Now, pick some particular line of magnetic flux that penetrates the pink region. If it passes through the pink region then there are two possibilities for how it returns to its source (completing the loop): either it comes back through the pink region, in which case it cancels itself out contributing nothing to the total count of flux penetrating the the pink region, or it comes back SOME OTHER WAY. The only other way back is through the “white space” that you see above, below, and to
the sides of the apparatus. Therefore if you errect a white curtain above, below, and to the sides of the apparatus, covering all the space you see that isn’t already pink (looking from your perspective like a photographic negative of the pink region), and anchored at its edges along the trace and plane precisely coincident with the edges of the pink soap bubble, you may rightly conclude that any flux that contributes to the total flux count in the pink region must also penetrate the white sheet. In other words, you can
count the flux passing through the pink region, or count the flux passing through the white sheet, either way you get the same answer. This property directly relates to the discussion above about the infinite plane partitioning space. As long as the pink and white surfaces, when combined, form an infinite partition of space, the total flux through that partition must be zero, ergo, the flux through the pink and white surfaces must be the same. This is what I think Andy was talking about when he said that if you extended the area of integration to infinity you could catch all the flux.

The total flux passing through the pink region in reaction to a current on the trace of 1 amp is defined as the
inductance of the circuit formed by the trace and its associated reference plane.

I hope this rather lengthy discussion helps you sort out some of the paradoxes associated with magnetic-field integration.

Buried in the definition of inductance is the assumption that current always assumes minimum-inductance distribution. We say, “Current always follows the path of least inductance”, or more precisely, “Current at high frequencies, if not altered by significant amounts of resistance, always assumes a distribution that minimizes the inductance of the loop formed by the signal and return paths”. If you put something in the way of your current that alters the distribution of current on the return path (like a hole in the reference plane), then the current assumes some alternate distribution which must necessarily raise the inductance of the configuration (moving to any distribution other than the minimum-inductance distribution must
necessarily raise the inductance).

Regarding your interest in the exact distribution of current problem. This analogy I’ve developed in the course of making up laboratory demonstrations for my new class on Advanced High-Speed Signal Propagation.

First replace your dielectric medium (the space between the trace and reference plane) with a slightly resistive material. I like to imagine salt water occupying that space. Leave the trace open-circuited at both ends, and apply 1-V DC to the trace. A certain pattern of current will flow through the salt water to the reference plane. I’ll bet you could draw a picture showing the pattern of current flow in this situation. Start with a cross-sectional view of the trace. Suppose you use 100 lines for the picture, each line representing a certain fraction of the total current. Each line emanates from the trace and terminates on the plane
(unlike magetic lines of force these current density lines have beginnings and endings). A great density of lines will flow directly between the trace and plane, with the lines feathering out to lower and lower densities as you work your way further from the trace. The lines always leave the surface of the trace in a direction perpendicular to the surface of the trace, and land perpendicular to the reference plane.

Here’s why I like this exercise: Your picture of the DC current flow exactly mimics the picture of lines of electric flux in a dielectric medium operated at high frequency. I find many people have no difficulty imagining how DC currents would behave in salt water–and it’s the same problem figuring out how AC currents behave in a dielectric medium.

Now we get to the part of this discussion about the density of current in the reference plane. Your electric-field picture shows a great density of current flowing from trace to plane at a position directly underneath the trace, and less and less density of current flowing to positions on the plane remote from the trace. This picture shows precisely how the current gets from trace to plane (i.e., it flows through the parasitic capacitance between trace and plane). If you assume that once the current arrive on the plane it
flows parallel to the trace (making the cross-sectional picture the same at each position along the trace, as
required by symmetry), then you can see that the picture also shows the density of current flowing on the plane as a function of position. Most of the current flows on the reference plane right under the trace, with less and less as you move away from the trace (it happens to fall off approximately quadratically for microstrips, even faster for striplines).

Of course, you are going to want to know “why” current should behave in such a manner. The principle in question here is the “minimum energy” principle. My recollection of Maxwell’s equations (specifically I *think* it’s the ones that say the Laplacian of both electric and magnetic fields are zero within source-free regions) is that the distributions of charge and current in a statics problem fall into a pattern that satisfies all the boundary conditions around the edges of the region of interest, satisfies the Laplacian conditions in the middle, AND ALSO just happens to store the *minimum* amount of energy in the interior fields. In other words, you aren’t going to get huge, unexplained, spurrious magnetic fields in the middle of an otherwise quiet region (unless you believe in vaccuum fluctuations, which is a different subject entirely…).

The stored energy for inductive problems is: E = (1/2)*L*(I^^2), where where L is the system inductance and
I^^2 is the total current squared. As you can see, stored magnetic energy E and inductance L vary in direct proportion to one another. Therefore, the distribution of current on the reference plane that minimizes the total stored magnetic energy and the distribution of current that minimizes the inductance are one and the same.

In answer to what might logically be your next question, “Why do electromagnetic fields tend towards the
minimum-stored-energy distribution?”, I can only say that I’m not sure anyone really knows — we just observe that this is the way nature seems to operate. Perhaps someone more well-versed in electromagnetic theory can provide an answer.

By assuming the current is *NOT* in the minimum-energy distribution you can demonstrate the existance of a mode of current that leads to a lower-energy state, but that demonstration would convince you of the absurdity of the non-minimum energy situation only if you also intuitively believe that nature is not absurd. Further discussion of *that* issue is probably best left to physicist-philosophers.

I hope this discussion is helpful to you, and doesn’t just stir up a lot of other doubts.

For further reading, try the following articles: “High-Speed Return Signals”, “Return Current in Plane”, “Proximity Effect”, “Proximity Effect II”, “Proximity Effect III”, and “Rainy-Day Fun”, (see http:\\sigcon.com, under “archives”, look for the alphabetical index).

Best regards,
Dr. Howard Johnson, Signal Consulting Inc.

As they say, interesting things happen when you are away from your mail.  For a moment, I wondered if the list administrator has changed!

John,

You know, Lawrence is a good friend of mine. He never mentioned about  your impressive language skills. Readers might be wondering why I am  talking about Lawrence instead of Henry. Simple. John and I worked at a  company called Cognigine and John used to report to Lawrence. Enough  said. Oh, let me make sure, are you the same John Lipsius?

You seem to agree that there is some confusion. Novice or expert, it is important to sort out any confusion. If I am not looking at issues  correctly, I better get the right perspective and this list is a good place. We all know about blindspots.

I consider myself a novice and tomorrow SI depends on today novices. So,  novices should not be intimidated by confusion. For those who find this thread confusing or annoying, there is the delete button.

There is some useful contribution you can make(unless you think it is a wasted effort). Please give that physics or microwave text and illustrations. I will do my dot product and perhaps some cognitive  integration also.

BTW, are we not concerned about changing currents?

Sainath

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From: “john lipsius

> BTW, are we not concerned about changing currents?

thank you, my point is thus proven (as I gambled it would be, by following that hard to
find but always-present “path of minimum energy”

…amazing)
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Dear Howard,

I appreciate your participation, time and views. I have some issues but let us consider the most important one. I’ve reproduced portions of your
text(in quotes) for discussion convenience. Any text without quotes is mine. It’s unusual and uncomfortable to read, but please bear with me.

“The stored energy for inductive problems is: E =(1/2)*L*(I^^2), where where L is the system inductance and
I^^2 is the total current squared. As you can see, stored magnetic energy E and inductance L vary in direct proportion
to one another. Therefore, the distribution of current on the reference plane that minimizes the total stored magnetic
energy and the distribution of current that minimizes the inductance are one and the same.”

For a microstrip, “Most of the current flows on the reference plane right under the trace, with less and less as
you move away from the trace” as shown in Fig. 5.3 in Black Magic book.

Using above formula and figure, “the distribution of current on the reference plane that minimizes the total stored magnetic
energy” occurs near the tail portions(away from the trace). This distribution is “one and the same” as “distribution of current that
minimizes the inductance”.

So, it appears to me that the path of least inductance for the return current is away from the trace where the current is minimum.

However, it is generally believed that the path of least inductance for the return current is on the reference plane right under the trace.
Using above formula and figure and the fact that “stored magnetic energy E and inductance L vary in direct proportion to one another”, right
under the trace, current is maximum => stored energy is maximum => inductance is maximum.

What’s wrong with my line of reasoning?

Sainath
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John,
What did you want us to understand from this message? It looks plain English. But, what does it convey?

I didn’t know that you gambled with technical issues.

Sainath

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Dear Sainath,

Let’s work for a minute on your concept of the “path of least inductance”.

I think a better wording here would be the “distribution of Imagine you have a long, straight pcb trace carrying a certain amount of signal current.

Underneath that trace I want you to construct not a plane, but an array of wires (kind like a ribbon cable). Place the wires on a very fine spacing so that (in the limit) they approximate a plane, but keep them as individual wires.

Now connect an individual current generator to each of the return wires. With such an arrangement you can FORCE any distribution of return current that you want. The current (in the return wires) always flows parallel to the signal trace, as it would (by symmetry) in a solid-plane situation.
[NOTE: here I'm just thinking about current in the return plane for a long, straight trace configuration. Towards the ends of the trace there are surely some deviations from straight-line flow which for now I will simply ignore].

Now I want you to adjust the current generators to energize only one of the return wires at a time. In each case, record the total magnetic flux (i.e., inductance) of the configuration using just that one return wire. You will find that the particular return wire that generates the least inductance is the one directly underneath the trace. Concentrating all the return current on that one wire, however, does not create the “path of least-inductance”.

To find the path of least inductance (actually, the return-current “distribution of least inductance”) you must
try ALL POSSIBLE distributions of return currents (with the constraint that the sum of return currents must equal the signal current in each case), and record the total magnetic flux for each distribution. You will find that the particular distribution of return current that generates the least inductance looks like the curve shown in Figure 5.3, page 191, of “High-Speed Digital Design: A Handbook of Black Magic”.

If you choose any distribution of current OTHER than the “distribution of least inductance” then I can always choose another distribution that has less overall inductance. How do I do this, you may wonder? There are several ways. The way nature does it is to make use of a theorem that says that if you are NOT using the distribution of least inductance then magnetic lines of flux must exist that penetrate the return plane (in your case, these lines penetrate your dense carpet of return wires). These magnetic field lines create circulating currents (eddy currents) in your wires that tend to modify your distribution of current, always making it more like the “distribution of least inductance”. If you use individual current sources on each wire you can prevent the eddy currents from having an effect, but if you connect the wires together at the ends of the ribbon the eddy currents will rapidly cause the wires to attain the “distribution of least inductance”. That’s what happens in a solid highly-conductive plane.

If, on the other hand your plane is not so conductive (perhaps it has some significant resistance) then the
resistance of the plane interferes with the eddy currents in such a way that the eddy currents may not be sufficiently powerful to form the “distribution of least inductance”. That happens in DC power distribution problems, where I’m sure you’ve heard the old adage “current follows the path of least resistance”. In the context of current flowing in a solid plane the “path of least resistance” is not be simply a straight line of infinitely thin width directly from source to load. Instead, the current spreads out, taking maximum advantage of all the available copper in the plane.
The distribution of current in the solid plane that minimizes the power dissipated in the plane is called the
“path of least resistance” (actually, it should be more properly called the “distribution of least resistance”).

In DC resistively-dominated problems the force that casues redistribution of current in the plane is the electric-field potential. In magnetically-dominated problems the force that causes redistribution of current in the plane is the magnetic-field potential (associated with eddy currents). In both cases the current spreads out, assuming not just one path but a distribution of pathways. For typical pcb geometries using 1/2 oz. copper planes the frequency at which the inductive (magnetic) effects supersedes the resistive (DC) effects is on the order of approximately 1 MHz. It is possible using matrix mathematics along with the concept of mutual inductance to derive the distribution of least inductance, but that’s not how nature
does it. In a natural setting the current re-distributes itself according to the action of localized eddy currents.

You are indeed correct that the “distribution of least inductance” includes the current flowing at positions remote from the trace.

I can provide one analogy that may help you understand the cooperative behavior of current both underneath and remote from the trace.  Suppose I solder together two resistors in parallel. Let one of them be 1000 ohms, and the other be 1,000,000 ohms. The effective parallel impedance will be 999.000999000999000… ohms.  What in this case would you call the “path of least resistance”?  Surely it is true that MOST of the current flows through the 1000-ohms resistor, but PART of the current also flows through the 1,000,000 ohms resistor. If you force a current of 1 mA through the parallel combination you will develop a voltage of 0.999000999000… volts, and observe currents of 0.999000999000… mA and 0.000999000999000… mA in the two resistors, respectively. Give a name to this distribution of current, calling it distribution “A”.

Suppose now you connect individual current sources to the individual resistors so you can adjust the current separtely in each. I claim that, of all possible distributions of current adding up to 1 mA, the particular distribution “A” is the one that minimizes the total dissipated power. Distribution “A” also happens to have the property of generating the SAME voltage across both resistors. This example is highly analogous to the “distribution of least inductance”, where the distribution of least inductance has the property of minimizing the total magnetic flux (i.e., minimizing inductance) AND ALSO has the property of generating the same voltages at the ends of every wire (technically, this is the same as ensuring that no magnetic flux penetrates the solid reference plane).

The same general reasoning, by the way, applies to the distribution of current around the periphery of the pcb trace itself, and at every point on all other conductive objects near your trace.

I do wish we could have a chance to talk this over in person, as I sense you have many questions. I’ll be in San Jose right after labor day.  Write to me at howiej@xxxxxxxxxx if you would like to arrange a time to
meet.

The mathematics associated with finding the path of least inductance are discussed further in my articles, “High-Speed Return Signals”, “Return Current in Plane”, “Proximity Effect”, “Proximity Effect II”, “Proximity Effect III”, and “Rainy-Day Fun”, (see http:\\sigcon.com, under “archives”, look for the alphabetical index).

Best regards,
Dr. Howard Johnson, Signal Consulting Inc.,
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selected si-list topics ,

Final note on XTK ( Cross Talk)

March 13th, 2009

I think I see where the confusion about cross talk is coming from in this thread. Once again, I think it stems from the words we are using. In this thread, we have been discussing three different topics, yet, using the same terms of “cross talk”.

The actual cross talk voltage noise at the near and far end of an adjacent quiet line is one set of terms. These voltage signatures depend on the intrinsic coupling between the lines, and the extrinsic line features of length, the terminations (due to the impact of the reflected noise) (which Scott McMorrow pointed out off line) and signal magnitude and rise time, and as Yuri and other have pointed out, the losses.

Then there is the near end cross talk coefficient (NEXT) and the far end cross talk coefficient (FEXT). These are generally defined in a transmission line environment where the ends of all the lines are terminated, so as to not compound the complexity of the problem with the impact from the reflections of both the signals and the noise. The NEXT depends on the intrinsic line parameters, and provided the coupling length is longer than the saturation length, not on the rise time or length. The FEXT depends on intrinsic line parameters and the line length and the rise time.

Finally, there are the intrinsic coupling coefficients, related to the relative distributed coupling capacitance per length between the two transmission lines, to the capacitance per length of the signal line to its return and the distributed loop mutual inductance per length to the loop self inductance per length of the signal line. Granted, this is as per the circuit’s model, as an approximation to the more accurate field’s model.

It is absolutely correct that the NEXT is related to the relative capacitive coupling + the relative inductive coupling, while the FEXT is related to the difference between the capacitive and inductive coupling. This might lead one to believe that NEXT will always be > FEXT. However, the FEXT also scales with the coupling length and inverse with the rise time, while the NEXT does not. This means that for long lines, and short rise times, FEXT can be >> NEXT.

How long and how short..it depends. Knowing the coupling terms, it is easy to calculate how long and how short to have FEXT > NEXT.  If you want the details, see the chapter in my book on cross talk.

Hope this helps.

–eric

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Dr. Eric Bogatin, Signal Integrity Evangelist
Bogatin Enterprises

Eric and All,

Excellent summary on crosstalk.

Just one minor clarification to the statement:
” However, the FEXT also scales with the coupling length and inverse with the rise time, while the NEXT does not.”

In the time domain, both NEXT and FEXT have saturated and unsaturated regions.  Both NEXT and FEXT scale with length and (inversely) with aggressor rise-time in their unsaturated region.  NEXT saturates at the backward crosstalk coefficient, whereas FEXT saturates practically at full coupling.  Full coupling finds very good applications in microwave and optical applications, but in high speed digital circuits, where crosstalk is mostly an unwanted bad side effect, we want to stay clear from the saturated far end crosstalk region.

Regards,

Istvan

selected si-list topics ,

How not to feel exhausted after long hours of working on Computer

March 7th, 2009

Working  long hours  on computer leads to feeling of having exhausted and lacking energy at the end of the day. The lack of energy leads to lack of concentration. The lack of concentration leads to unfocussed effort. The unfocussed effort leads to wandering away from the actual work and instead spend time on surfing the internet, checking emails, seeing stock market, reading news, participating in unnecessary forums and discussion, porns.

So, how to we overcome this fatigue, increase productivity ? Here are few steps.

1. Keep your spinal chord straight while working. At time your spinal chord will become curved while you are concentrating on work. Make is straight as soon as you remember. Make a determination at the start of day that keeping spinal chord straight is more important  than the work itself.

2. At every two hour take a break of 10 minutes. Take deep breath for 5 minutes, then close eyes for 5 minutes and begin work again. You reduce the time worked on by 10%, but you increase your efficiency by 10%. The major gain will be, you will feel energetic when you are back at home.

3. While working, try to feel your body or your breathe. This is tough part not because the process is difficult but because you will not know when you lapse and start focusing on the work in place of your body. Simultaneous attention on work and the breathe will take time to master.

4. Try to finish the work in 8 hours. Try not to overstay.

5. If you are programming person, instead directly jumping to coding, close your eyes, and meditate for 10 minutes on how to solve  the problem and what should be overall approach. Write them  in pencil and paper in few sentences and then proceed.

Remember your health is more important than your job.

Uncategorized

Designing for EMI Compliance

March 1st, 2009

1 Designing for EMI Compliance

Once the product is tested at the lab and its functionality is as expected, it is time to take the product for the EMI/EMC compliance test. If you want to sell your product, it must obey some legal obligations. In United States of America FCC ( Federal Communications Commission) specifies the limits of maximum amount of radiation a product can generate. Canada has DOC, and Europe has EMC-Regulation, which must be met. Other countries have similar regulations.

The contents are selected excerpts from the Book Signal Integrity for PCB Designers.

FCC has two classes of products based upon the amount of radiation they are allowed. The radiation limit for Class A products are less stringent. Class A products are those that are meant to be used only in industrial and manufacturing environment. A product designated as Class A is not intended to be sold in home or residential areas. They are allowed to radiate more. The radiation limits for Class B products are more stringent. Class B products are those that are meant to be used in home and office environment.

For Class A products, the radiated electric fields are measured at a distance of 10 meters from the product. The Table below gives the maximum radiated field strength for class A products.

Table 131: FCC Class A Emission Limits

Frequency (MHz)

Electric Field, µV/m

30-88

90

88-216

150

216-960

210

>960

300

Figure 13 1 - FCC Class A Certification Limits – Field Strength at a distance of 10 meters

For Class B, the radiated electric fields are measured at a distance of 3 meters from the object.

Table 132 - FCC Class B Emission Limits

Frequency (MHz)

Electric Field, µV/m

30-88

100

88-216

150

216-960

200

>960

500

Sometimes the Emission levels are mentioned in dBµV/m. The chart below gives the emission limits in dBµV/m.

The contents are selected excerpts from the Book Signal Integrity for PCB Designers.

Table 133 - Class B Emission Limits in dBµV/m

Frequency (MHz)

Electric Field, dBµV/m

30-88

40

88-216

43

216-960

46

>960

54

Following formula can be used for conversion from µV to dBµ

Figure 13‑2 - FCC Class B Certification Limits – Field Strength at a distance of 3 meters.

On the first day you take your equipment to the EMI laboratory, the lab personal will run a quick radiation test. It will test for any unintentional radiation from your equipment. If your equipment has been designed well it should be within the specified limits. Here is how a typical curve may look like.

We will briefly review the major sources of the Electromagnetic Radiation in a typical design.

The contents are selected excerpts from the Book

1.1.1 Cables

When a driver sends a current down a PCB trace, most of the returning signal current flows on the plane directly beneath the signal trace. However, in an attempt to find the minimum inductance path, some of the returning signal spread out over the plane. We call this stray current. When this signal, for example, crosses a via or an inter board connector, there is a change in returning current path by way of change in power plane. This sudden change leads to significant increase in the stray current. A cable carrying a current, similarly has a return path. If however, there is an current that does not return, it becomes a common mode current. Common mode currents radiate. Common mode currents in cables outside the box are most common sources of the EMI failures.

1.1.2 Field induced in cables

If there is a trace carrying high speed signal, it can induce the voltage in the trace in the nearby trace. If there is a cables attached to this trace is going out of the board, it can result in significant radiated emissions. This mechanism is illustrated in Figure below.

All traces that go to a connector and having finite cable length out of the board must, therefore be kept away from high speed signals.

1.1.1 Clock Oscillators

Next to cables, Clock oscillators are major sources of EMI. Cycle after cycle clock oscillator send signals and superimpose upon each other. Observed on spectrum analyzers, these signals are observed as radiation. In most cases, the harmonics of these clock oscillators are also observed.

1.1.2 Mismatched Transmission Line

Transmission lines A mismatch transmission line will increase EMI. A matched transmission line will minimize it. Mismatch in transmission lines die to the via, layer change leads to increase in stray current. A matched transmission line reduces probability of radiation besides improving signal integrity.

1.1.3 Long Traces

High speed traces connecting clock and data lines are sources of radiation. The amount of the radiation will depend upon the length of the wires. Longer the traces, more is the chance of the radiation. In special cases, if these length are multiples of the certain frequencies, it can lead to resonance condition and source of radiation.

1.2 How to Reduce EMI

There are preventive as well as curative methods available at the hands of designers. Pay attention to the preventive methods during the design stages. As a real world engineer you should also be aware of the methods and patches that can be applied to a failing board to make it pass EMI test.

1.2.1 Match the Transmission Line and Termination

Transmission lines radiate. The amount of the radiation will depend upon several factors. This includes, return path discontinuities and stray current when changing the layer. A mismatched transmission line and mismatched termination increases the emission.

1.2.2 Use Short Clock Lengths where possible

Even if your board area is large, do not unnecessarily spread out components. Spreading out components, especially the high speed clock signals will lead to longer transmission lines and will tend to create more EMI.

1.2.3 Use Differential Signaling

In differential signaling , the two wires carry signals in opposite directions. One of the wires carries a current which is opposite to the direction of the current in the other wire.

The magnetic field generated by one wire has a direction opposite to that of the field generated by the other wire. Any radiation field generated by one of the two wires is canceled by the radiation field generated by the other wire. It essentially means that the radiation by a differential pair is substantially less.

To take advantage of the separation between the differential pair is as small as possible. If we increase the separation between the traces, then the antenna close to the positive pair will have more field strength due to the positive pair than to the negative pair. The result will be a net electric field and the resulting EMI. Therefore, the differential pair should be routed as close to each other as possible.

In order to take advantage of the radiation cancellation from differential signaling, the two signal pairs must be routed symmetrically and their length must match as close as possible. If their lengths are not equal or they are not routed symmetrically, the radiation pattern will not cancel completely.

Another factor we must keep in mind is that the common mode radiation created by the common mode currents in the two wires do not cancel – rather they add up. Therefore there will not be any reduction in the radiated field due to the common mode current. We must however, note that creating any kind of imbalance in the differential pairs increases the common mode voltage and current and therefore increases the radiated emission.

Practically speaking, the differential signaling will improve EMI performance over the corresponding single ended signaling because of the fact that the common mode typical voltage level is far less than the corresponding minimum common mode level that would have been possible with the single ended signaling.

The contents are selected excerpts from the Book Signal Integrity for PCB Designers.

1.2.4 Use Higher value of Series Resistor

The amount of the radiation from a high speed trace will depend upon the amount of the current flowing in the trace. If we need to reduce the EMI, we should reduce the amount of the current flowing, especially, in the clock circuits. This can often be achieved by increasing the series resistance. Increasing the series resistance will decrease the current and thereby reduce the amount of the radiation. Another effect the series resistance has is that – it dampens the signal which in turn reduces EMI. We must ensure through the simulation that the higher series resistance does not lead to the signal degradations.

Usually, increasing the series resistance will show a slightly dampened waveform at the receiver. Once you have carried out simulation for perfectly matching value of the series resistance, extent the simulation experiment for higher value of the series resistance. There will be ranges of values of the higher series resistance which will give the acceptable signal at the receiver. If you care about EMI, select a series resistance at slightly higher than the nominal value.

If you can, try to simulate not only for the voltage level at the receiver, but also the current waveform in the trace. Increase the series resistance and try to see if it leads to substantial decrease in the current amplitude without any substantial degradation of the voltage waveform at the receiver.

1.2.5 Use Stripline over Microstrip for Critical Nets

When a high speed signal is propagating, its electromagnetic fields are confined within the ground and power planes. In case of the microstrip the electromagnetic fields are confined between the trace and the return ground path. In case of the stripline, the electromagnetic fields are confined between the surfaces. Striplines, therefore radiate less than the microstrips. If there is a known clock net that seems to fail in EMI or is likely to fail EMI, it should be routed as stripline in place of microstrip. The electromagnetic waves are well contained within the ground and power planes in case of striplines and therefore there is at least some improvement over the corresponding microstrip structure. It is important that the we should consider other aspects of the design. Striplines do take up more space and there is more signal loss during propagation.

1.2.6 Board level Shielding

If the radiation can not be contained using all the novel methods, we must make a provision of shielding. There are many ways shielding can be achieved. If we know a particular area of the circuit that is found to radiate more than other areas then we can enclose that area of the PCB using metallic enclosures. As a PCB designer you should work in advance to make a place for fitting the mechanical enclosures. Most of the RF circuits have metallic enclosure not only to reduce EMI but also to keep it safe from external radiations.

Consider a project which has a very small life – say nine months. The profit margin for the product is high. You do have a second chance to design, but you will loose a substantial amount of revenue. For such product, making a provision for metallic shield may make sense if the space allows.

Shielding should, however, be a secondary choice. Attempt should be made to make the non RF products pass EMI tests without the shielding.

1.2.7 Use Lower Voltage Swing

Higher the voltage level more is the current, more is the radiated emissions. Reducing the voltage level reduces the amount of the current flowing in the structures and therefore reduces the EMI. If you have a choice during the architecture stage of design, prefer the one that uses lower voltage levels to operate. If you have a clock oscillator and if you have a choice, use a lower voltage level to operate it.

Use of lower voltage also reduces the power consumption. If you reduce the voltage level by half, you reduce the power consumption by one fourth. If you are using external oscillators for your system you should be able to find different parts in the series operating at different voltages. You should choose the one that uses power supply lowest voltage, still being sufficient for your design.

As you lower the voltage swing your signal becomes more susceptible to noise. To overcome susceptibility to noise, you can use a differential signal, if your design allows. Otherwise keep the critical signal away from other high speed traces to make it less susceptible to cross talk noise.

1.2.8 Do not route Critical Signals near edges

All critical clock signals should not be routed at the edge of the Board. When the traces are routed in the inner section of PCB, the return signal flows mostly under the signal on the power planes. There is little, if any, stray current at the edges of the board. When the critical signals are routed at the edges of the board, the stray currents are at the edges of the board, resulting in more radiation.

1.2.9 Use of Metallic Shields or Enclosures

One of the ways for a equipment that would otherwise fail FCC test is to enclose it in metallic enclosure. Most of the personal computers will fail FCC test if they are not enclosed in a metallic enclosure. By using metallic shielding, the amount of radiation is reduced.

Metallic enclosure should not have gaps in between them to be most effective. Ideally they should not be any slots or holes. If there are slots or holes, they should be as small as possible. The thickness of the shield is of secondary importance.

At frequencies less than 100 MHz, you will need magnetic materials for the enclosures to be more effective. At higher frequencies the small openings will allow high frequency radiation to escape through the openings.

The designers sometimes make a provision for the metallic enclosure in the beginning of the design. Computational products with very high IO frequencies have more radiations and are more likely to fail in FCC tests. The metallic enclosures come at their rescue.

1.2.10 Shield Conductive Coating

In many cases, the plastic enclosure in place of metallic enclosure is decided to be used in the beginning of the design. If the equipment fails the FCC test, then metallic chemical coating can be used in the inner side of the plastic enclosure. A coating one to two mils thick can provide an attenuation of 20 dB or more. This should be sufficient to make most of the failing equipment to pass EMI test. Super Shield from MG Chemicals is one such product.

This is not to suggest that this method should be used as a general practice. In fact, as an electrical designer we must strive to design a product that does not need a shield coating or a metallic enclosure for that matter. The business requirement, however, may dictate that we do use them when we have no other choice.

1.2.11 Use of Spread Spectrum Oscillators

In the EMI analysis you will find that your equipment fails at a certain well defined frequency and its harmonics. If you trace the source of these oscillations, they may correspond to a particular oscillator. These oscillators have a well defined frequency. Observed in spectrum analyzers they will have a well defined peak amplitudes at a well defined frequencies.

One way to reduce the peak amplitude at the well defined frequency is to use spread spectrum oscillator. A frequency of spread spectrum oscillator varies back an forth around a nominal central frequency. The amplitude of both the fundamental and the harmonics is reduced by making the clock frequency vary in time. The energy remains constant, a varying frequency broadens the fundamental and harmonics and decreases their amplitudes.

The contents are selected excerpts from the Book Signal Integrity for PCB Designers.

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