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AMBA AXI Protocol

August 18th, 2015

The AMBA AXI protocol supports high-performance, high-frequency system designs.

The AXI protocol:

  • is suitable for high-bandwidth and low-latency designs
  • provides high-frequency operation without using complex bridges
  • meets the interface requirements of a wide range of components
  • is suitable for memory controllers with high initial access latency
  • provides flexibility in the implementation of interconnect architectures
  • is backward-compatible with existing AHB and APB interfaces.

 

The key features of the AXI protocol are

  • Separate address/control and data phases
  • Support for unaligned data transfers, using byte strobes
  • Uses burst-based transactions with only the start address issued
  • Separate read and write data channels, that can provide low-cost Direct Memory Access (DMA)
  • Support for issuing multiple outstanding addresses
  • Support for out-of-order transaction completion
  • Permits easy addition of register stages to provide timing closure.

The AXI protocol includes the optional extensions that cover signaling for low-power operation.

AXI Architecture:-

The AXI protocol is burst-based and defines the following independent transaction channels:

  • read address
  • read data
  • write address
  • write data
  • write response

An address channel carries control information that describes the nature of the data to be transferred. The data is transferred between master and slave using either:

  • A write data channel to transfer data from the master to the slave. In a write transaction, the slave uses the write response channel to signal the completion of the transfer to the master.
  • A read data channel to transfer data from the slave to the master.

The AXI protocol:

  • Permits address information to be issued ahead of the actual data transfer
  • Supports multiple outstanding transactions
  • Supports out-of-order completion of transactions.

Block Diagram of master slave module

 

-AXI

Channel architecture of write operation:

AXI1

Write transaction uses the write address, write data, and write response channels.

Write data channel:-

The write data channel carries the write data from the master to the slave and includes:

  • the data bus, that can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide
  • a byte lane strobe signal for every eight data bits, indicating which bytes of the data are valid.

Write data channel information is always treated as buffered, so that the master can perform write transactions without slave acknowledgement of previous write transactions.

Write response channel:-

A slave uses the write response channel to respond to write transactions. All write transactions require completion signaling on the write response channel.

Channel Architecture of Read Operation:

AXI2

Read transaction uses the read address and read data channels.

Read and write address channels:-

Read and write transactions each have their own address channel.

The appropriate address channel carries all of the required address and control information for a transaction.

Read data channel:-

The read data channel carries both the read data and the read response information from the slave to the master, and includes:

  • the data bus, that can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide
  • a read response signal indicating the completion status of the read transaction.

 

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