The i.MX6 boards that come in several flavors have been found to fail in extreme memory tests. One of the quick ways to fix it is to Calibrate the DDR3 memory and see if this fixes the issue. We will outline the steps that has been verified to work.

**The procedure outlines for the calibration of DDR in MX6. **

Step 1 : Downloaded DDR stress tester from

Navigate to the freescale post at https://community.freescale.com/docs/DOC-96412

We will used the procedure where we can calibrate using Serial Ports. We may look at the USB method at some other time. The file to use is DDR_Stress_Tester_V1.0.2_UART1_for_SDboot&JTAG.zip. Download and unzip this file and navigate to find the file named DDR_Stress_Tester_V1.0.2_UART1\ddr-stress-test-mx6dq.bin.

Copy this file to your SD Card using the procedure in < a href ="http://referencedesigner.com/blog/transferring-kernel-in-i-mx6-android-system-using-adb/2359/"> this blog

2. Boot the board, stop at u-boot and load the DDR stress test file using

U-Boot > ext2load mmc 0:1 0x907000 /ddr-stress-test-mx6dq.bin

U-Boot > go 0x907000

Note that this assumes SD Card is on ext2 filesystem. The original command for fat SD Card

as mentioned in freescale site is

U-Boot > fatload mmc 2:1 0x907000 ddr-stress-test-mx6dq.bin

U-Boot > go 0x907000

3. Extend Serial Ports on Pins CSI0_DAT10 and CSI0_DAT11 of your board. These pins will be used as UART ports that will give the output when booting.

At this stage you can get the calibration results

******************************

DDR Stress Test (1.0.2) for MX6DQ

Build: Dec 10 2013, 14:26:05

Freescale Semiconductor, Inc.

******************************

=======DDR configuration==========

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 14, col size: 10

Chip select CSD0 is used

Density per chip select: 1024MB

==================================

What ARM core speed would you like to run?

Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz

ARM set to 800MHz

Please select the DDR density per chip select (in bytes) on the board

Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB

For maximum supported density (4GB), we can only access up to 3.75GB. Type 9 to select

this

DDR density selected (MB): 512

Calibration will run at DDR frequency 528MHz. Type ‘y’ to continue.

If you want to run at other DDR frequency. Type ‘n’

DDR Freq: 528 MHz

Would you like to run the write leveling calibration? (y/n)

Please enter the MR1 value on the initilization script

This will be re-programmed into MR1 after write leveling calibration

Enter as a 4-digit HEX value, example 0004, then hit enter

0004 You have entered: 0x0004

Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x001E001E

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x002F0023

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x002C0036

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x001D0034

BYTE 0:

Start: HC=0x02 ABS=0x18

End: HC=0x04 ABS=0x4C

Mean: HC=0x03 ABS=0x32

End-0.5*tCK: HC=0x03 ABS=0x4C

Final: HC=0x03 ABS=0x4C

BYTE 1:

Start: HC=0x01 ABS=0x68

End: HC=0x04 ABS=0x40

Mean: HC=0x03 ABS=0x14

End-0.5*tCK: HC=0x03 ABS=0x40

Final: HC=0x03 ABS=0x40

BYTE 2:

Start: HC=0x01 ABS=0x58

End: HC=0x04 ABS=0x28

Mean: HC=0x02 ABS=0x7F

End-0.5*tCK: HC=0x03 ABS=0x28

Final: HC=0x03 ABS=0x28

BYTE 3:

Start: HC=0x01 ABS=0x5C

End: HC=0x04 ABS=0x3C

Mean: HC=0x03 ABS=0x0C

End-0.5*tCK: HC=0x03 ABS=0x3C

Final: HC=0x03 ABS=0x3C

BYTE 4:

Start: HC=0x02 ABS=0x14

End: HC=0x04 ABS=0x68

Mean: HC=0x03 ABS=0x3E

End-0.5*tCK: HC=0x03 ABS=0x68

Final: HC=0x03 ABS=0x68

BYTE 5:

Start: HC=0x02 ABS=0x14

End: HC=0x04 ABS=0x50

Mean: HC=0x03 ABS=0x32

End-0.5*tCK: HC=0x03 ABS=0x50

Final: HC=0x03 ABS=0x50

BYTE 6:

Start: HC=0x01 ABS=0x50

End: HC=0x04 ABS=0x0C

Mean: HC=0x02 ABS=0x6D

End-0.5*tCK: HC=0x03 ABS=0x0C

Final: HC=0x03 ABS=0x0C

BYTE 7:

Start: HC=0x00 ABS=0x7C

End: HC=0x04 ABS=0x44

Mean: HC=0x02 ABS=0x60

End-0.5*tCK: HC=0x03 ABS=0x44

Final: HC=0x03 ABS=0x44

DQS calibration MMDC0 MPDGCTRL0 = 0x4340034C, MPDGCTRL1 = 0x033C0328

DQS calibration MMDC1 MPDGCTRL0 = 0x43500368, MPDGCTRL1 = 0x0344030C

Note: Array result[] holds the DRAM test result of each byte.

0: test pass. 1: test fail

4 bits respresent the result of 1 byte.

result 00000001:byte 0 fail.

result 00000011:byte 0, 1 fail.

Starting Read calibration…

ABS_OFFSET=0x00000000 result[00]=0x11111111

ABS_OFFSET=0x04040404 result[01]=0x11111111

ABS_OFFSET=0x08080808 result[02]=0x11111111

ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111

ABS_OFFSET=0x10101010 result[04]=0x11111111

ABS_OFFSET=0x14141414 result[05]=0x11011111

ABS_OFFSET=0x18181818 result[06]=0x01011010

ABS_OFFSET=0x1C1C1C1C result[07]=0x00011000

ABS_OFFSET=0x20202020 result[08]=0x00011000

ABS_OFFSET=0x24242424 result[09]=0x00010000

ABS_OFFSET=0x28282828 result[0A]=0x00010000

ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000

ABS_OFFSET=0x30303030 result[0C]=0x00000000

ABS_OFFSET=0x34343434 result[0D]=0x00000000

ABS_OFFSET=0x38383838 result[0E]=0x00000000

ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000

ABS_OFFSET=0x40404040 result[10]=0x00000000

ABS_OFFSET=0x44444444 result[11]=0x00000000

ABS_OFFSET=0x48484848 result[12]=0x00000000

ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000

ABS_OFFSET=0x50505050 result[14]=0x00000000

ABS_OFFSET=0x54545454 result[15]=0x00000110

ABS_OFFSET=0x58585858 result[16]=0x00100110

ABS_OFFSET=0x5C5C5C5C result[17]=0x00101110

ABS_OFFSET=0x60606060 result[18]=0x00101111

ABS_OFFSET=0x64646464 result[19]=0x01101111

ABS_OFFSET=0x68686868 result[1A]=0x11101111

ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111

ABS_OFFSET=0x70707070 result[1C]=0x11111111

ABS_OFFSET=0x74747474 result[1D]=0x11111111

ABS_OFFSET=0x78787878 result[1E]=0x11111111

ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111

MMDC0 MPRDDLCTL = 0x3E34363A, MMDC1 MPRDDLCTL = 0x3E3E344A

Starting Write calibration…

ABS_OFFSET=0x00000000 result[00]=0x10111111

ABS_OFFSET=0x04040404 result[01]=0x10110111

ABS_OFFSET=0x08080808 result[02]=0x10110011

ABS_OFFSET=0x0C0C0C0C result[03]=0x10100010

ABS_OFFSET=0x10101010 result[04]=0x00100000

ABS_OFFSET=0x14141414 result[05]=0x00100000

ABS_OFFSET=0x18181818 result[06]=0x00100000

ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000

ABS_OFFSET=0x20202020 result[08]=0x00000000

ABS_OFFSET=0x24242424 result[09]=0x00000000

ABS_OFFSET=0x28282828 result[0A]=0x00000000

ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000

ABS_OFFSET=0x30303030 result[0C]=0x00000000

ABS_OFFSET=0x34343434 result[0D]=0x00000000

ABS_OFFSET=0x38383838 result[0E]=0x00000000

ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000

ABS_OFFSET=0x40404040 result[10]=0x00000000

ABS_OFFSET=0x44444444 result[11]=0x00000000

ABS_OFFSET=0x48484848 result[12]=0x00000000

ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000

ABS_OFFSET=0x50505050 result[14]=0x00000000

ABS_OFFSET=0x54545454 result[15]=0x00000000

ABS_OFFSET=0x58585858 result[16]=0x00000000

ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000

ABS_OFFSET=0x60606060 result[18]=0x00001000

ABS_OFFSET=0x64646464 result[19]=0x00001000

ABS_OFFSET=0x68686868 result[1A]=0x01001000

ABS_OFFSET=0x6C6C6C6C result[1B]=0x01011111

ABS_OFFSET=0x70707070 result[1C]=0x01011111

ABS_OFFSET=0x74747474 result[1D]=0x11011111

ABS_OFFSET=0x78787878 result[1E]=0x11111111

ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111

MMDC0 MPWRDLCTL = 0x30383C3A,MMDC1 MPWRDLCTL = 0x4032483A

MMDC registers updated from calibration

Read DQS Gating calibration

MPDGCTRL0 PHY0 (0x021b083c) = 0x4340034C

MPDGCTRL1 PHY0 (0x021b0840) = 0x033C0328

MPDGCTRL0 PHY1 (0x021b483c) = 0x43500368

MPDGCTRL1 PHY1 (0x021b4840) = 0x0344030C

Read calibration

MPRDDLCTL PHY0 (0x021b0848) = 0x3E34363A

MPRDDLCTL PHY1 (0x021b4848) = 0x3E3E344A

Write calibration

MPWRDLCTL PHY0 (0x021b0850) = 0x30383C3A

MPWRDLCTL PHY1 (0x021b4850) = 0x4032483A

The DDR stress test can run with an incrementing frequency or at a static freq

To run at a static freq, simply set the start freq and end freq to the same value

Would you like to run the DDR Stress Test (y/n)?

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