Ethernet EMI Issue with i.MX6 SOM module

August 31st, 2015

One of the primary reason of failure of a product in EMI is the improper design of the return path for the critical high speed nets. When you are designing a product that has two or more modules, you need to pay special attention to the nets across the connector joining the modules.

All critical nets should have a nearby return ground signal.

As a practical example of incorrect design take a look at the following design of freescale’s i.MX6 based SOM module.

SOM-pinout

The SOM module looks as follows

SOM-pinout1

Carefully take a look at Pin number 1 called RGMII_REF_CLK. Where is the return ground pin ? It is nowhere near to be seen. The nearest ground pin is at Pin 63 – far away from the pin 1. When the signal returns it will create a big look and the signal will radiate profusely.

Since the SOM module has already been pre designed, it is tough to fix the issue later in the design. The only practical remedy to this problem is to remove some pins near pin 1 that are not used and make them ground pins. Another solution could be to create a metallic enclosure around the SOM module in the base board that uses this SOM module. Both the solutions are not clean. The ideal solution will be to re spin the SOM module and add ground pins near all the critical nets.

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Wifi and Bluetooth options on Freescale i.MX6

August 27th, 2015

If you are designing system that uses Freescale’s i.MX6, you have following options to include Wifi and bluetooth in your design

1. USB based solutions

Just use any of the stock tiny USB modules available in the market. You have the flexibility to choose anything you wish. From hardware design perspective it simplifies the things. You may want to choose the part that has drivers available. It is easy to verify. Typical cost is $9 each for Wifi and Bluetooth. On the downside, it is not the best solution if you wish to save board space. Also, the modules need to hang out of the board for antenna to work the best.

2. Broadcom based WM-BN-BM-02 module

The wandboard use the module from Edcom Technologies ( Taiwan / China )- that has part number WM-BN-BM-02. The module uses Broadcom 4325 chipset that includes Wifi, Bluetooth and FM Receiver. It is potentially a low cost option. Software support is potentially available from Wandboard community.

WM-BN-BM-02

3. TI Wi BLE

The TI-WI BLE module from LSR is based upon TI chipset and is priced moderately higher. This module is used in Nitrogen6 board from Boundary devices and therefore the drivers are available and working.

TI-WI-BLE

4. TI WiLink 8

A nice module from TI ( for example WL1801MODGBMOCT) is used in some of the designs based upon i.MX6. The price for these modules is in the range of $12 in volumes.

An ideal solution would have been a module similar to the WM-BN-BM-02 but the one that works on USB ports. There are many Broadcom modules available that work on USB port. This will simplify the hardware design, but it complicates the driver development.

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AMBA AXI Protocol

August 18th, 2015

The AMBA AXI protocol supports high-performance, high-frequency system designs.

The AXI protocol:

  • is suitable for high-bandwidth and low-latency designs
  • provides high-frequency operation without using complex bridges
  • meets the interface requirements of a wide range of components
  • is suitable for memory controllers with high initial access latency
  • provides flexibility in the implementation of interconnect architectures
  • is backward-compatible with existing AHB and APB interfaces.

 

The key features of the AXI protocol are

  • Separate address/control and data phases
  • Support for unaligned data transfers, using byte strobes
  • Uses burst-based transactions with only the start address issued
  • Separate read and write data channels, that can provide low-cost Direct Memory Access (DMA)
  • Support for issuing multiple outstanding addresses
  • Support for out-of-order transaction completion
  • Permits easy addition of register stages to provide timing closure.

The AXI protocol includes the optional extensions that cover signaling for low-power operation.

AXI Architecture:-

The AXI protocol is burst-based and defines the following independent transaction channels:

  • read address
  • read data
  • write address
  • write data
  • write response

An address channel carries control information that describes the nature of the data to be transferred. The data is transferred between master and slave using either:

  • A write data channel to transfer data from the master to the slave. In a write transaction, the slave uses the write response channel to signal the completion of the transfer to the master.
  • A read data channel to transfer data from the slave to the master.

The AXI protocol:

  • Permits address information to be issued ahead of the actual data transfer
  • Supports multiple outstanding transactions
  • Supports out-of-order completion of transactions.

Block Diagram of master slave module

 

AXI

Channel architecture of write operation:

AXI1

Write transaction uses the write address, write data, and write response channels.

Write data channel:-

The write data channel carries the write data from the master to the slave and includes:

  • the data bus, that can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide
  • a byte lane strobe signal for every eight data bits, indicating which bytes of the data are valid.

Write data channel information is always treated as buffered, so that the master can perform write transactions without slave acknowledgement of previous write transactions.

Write response channel:-

A slave uses the write response channel to respond to write transactions. All write transactions require completion signaling on the write response channel.

Channel Architecture of Read Operation:

AXI2

Read transaction uses the read address and read data channels.

Read and write address channels:-

Read and write transactions each have their own address channel.

The appropriate address channel carries all of the required address and control information for a transaction.

Read data channel:-

The read data channel carries both the read data and the read response information from the slave to the master, and includes:

  • the data bus, that can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide
  • a read response signal indicating the completion status of the read transaction.

 

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A list of Inexpensive Switching Regulators

August 15th, 2015

Almost all designs have at least one switching regulator. In this article we are giving out a list of inexpensive switching regulators and we expect that one of these will fit in your requirement.

All the components listed fit in the same package – SOIC8 with exposed pad.

SOIC-8-exposed-pad

1. Richteck USA RT7247AHGSP – $0.256 in 2.5K
– 2 Amp load, Input Range 4.5V to 18V, Output Voltage range 0.8V to 15V

2. Alpha & Omega Semiconductor AOZ1050PI – $0.29 in 3K
– 2 Amp load, Input Range 4.5V to 18V, Output Voltage range 0.8V to 15V.3

2. Diode Inc. AP3503FMPTR-G1 – $0.29 in 2.5K
– 3 Amp load, Input Range 4.5V to 18V, Output Voltage range 0.925V to 16.25V

3. Diodes Inc. AP65552SP-13 – $0.319 in 2.5K
– 5 Amp load, Input Range 4.5V to 18V, Output Voltage range 0.76V to 6V

The above three have the same pinout.

pinout-pmic

A typical application schematics

aaplication-schematics

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Parallel load Up Down Counter And Shift Register

August 15th, 2015

Let us understand up-down counter and shift register using one verilog with parallel load capability.

Features:
– 16 bit parallel load
– 16 bit programmable up-down counter
– Synchronous reset
– Programmable left-right shift
SINGNAL NAME       IN/OUT DESCRIPTION
Din                                  16 bit In For parallel load
nReset                             In Synchronous reset, active low
Clk                                    In Clock
Load                                 In Enables synchronous parallel load
Count                               In Enables counting
Shift                                 In Enables shift operation
Up                                    In Control for up counting
Dn                                    In Control for down counting
Right                                In Control for Right shifting
Left                                   In Control for Left shifting
Qout                                 16 bit Out For parallel readout
Sout-lsb                           Out Serial out – LSB
Sout-msb                         Out Serial out – MSB

Verilog Code:-

module counter_shift_reg ( nReset,
 din,
 Clk,
 Load,
 Count,
 Shift,
 Up,
 Dn,
 Right,
 Left,
 Qout,
 Sout_lsb,
 Sout_msb
 );

input nReset,Clk;
input Load, Count, Shift, Up, Dn;
input Right, Left;
input [15:0] din;

output Sout_lsb, Sout_msb;
output reg [15:0] Qout;
reg [15:0] temp;
wire Sout_lsb, Sout_msb;

////16 bit Programable counter
always @(posedge Clk) begin
 if(nReset==1'b0)
 Qout <= 0;
 else if(Load)
 Qout <=din;
 else if((Count && Up) == 1'b1 )
 Qout <= Qout +1;
 else if((Count && Dn) == 1'b1)
 Qout <= Qout - 1;
 else Qout <= Qout;
end

///Left shift and Right Shift
always @(posedge Clk) begin
 if(nReset==1'b0) begin
 temp <= 0;
 end
 else if(Load)
 temp <= din;
 else if ((Shift && Left)==1'b1) begin
 temp <= temp<<1;
 end
 else if ((Shift && Right) == 1'b1)
 temp <= temp >> 1;
 else
 temp <= temp;
end
assign Sout_lsb = Right ? temp[0] : 0;
assign Sout_msb = Left ? temp[15] : 0;
endmodule
 

Testbench:-

module counter_shift_tb;
output reg nReset,Clk;
output reg Load,Count,Shift,Up,Dn;
output reg Right,Left;
output reg [15:0] din;
input Sout_lsb,Sout_msb;
input [15:0] Qout;
counter_shift_reg counter_shift(nReset,din,Clk,Load,Count,Shift,Up,Dn,Right,Left,Qout,Sout_lsb,Sout_msb);
initial
Clk=1'b0;
always
#5 Clk = ~Clk;
initial
 begin
 $monitor($time,"nReset=%b,din=%b,Clk=%b,Load=%b,Count=%b,Shift=%b,Up=%b,Dn=%b,Right=%b,Left=%b,Qout=%b,Sout_lsb=%b,Sout_msb=%b",nReset,din,Clk,Load,Count,Shift,Up,Dn,Right,Left,Qout,Sout_lsb,Sout_msb);
 nReset=1'b0;
 #15 nReset=1;Load=1;din=16'b0000000000000001;
 #30 Load=0;Count=1;Up=1;Dn=0;Shift=0;Right=0;Left=0;
 #40 Load=1;din=16'b0000000000001111;Up=0;Count=0;
 #45 Load=0;Count=1;Up=0;Dn=1;Shift=0;Right=0;Left=0;
 #65 Load=1;din=16'b1000000000001111;
 #75 Load=0;Shift=1;Right=1;Up=0;Dn=0;
 #85 Load=1;din=16'b1111000000000001;Right=0;
 #95 Load=0;Shift=1;Left=1;Up=0;Dn=0;
 #1000 $finish;
 end
initial
 begin
 $dumpfile("counter_shift_tb.vcd");
 $dumpvars(0,counter_shift_tb);
 end
endmodule

Read more…

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Freescale i.MX6 Vs i.MX7

August 12th, 2015

Freescale had announced the i.MX7 series of ARM processors in 2013, however, it was not until mid of 2015 that it started giving out more details. We will ordinarily assume that i.MX7 is a more powerful successor of i.MX6, however, on a closer look, it does not really look like so. The MX7 seems to have been designed for an entirely different market segment that targets products requiring low power, more battery life and low to moderate processing and graphics power.

And therefore the i.MX7 is not a processing power house. It, in fact comes in two flavors – one with Single core ( 800 MHz) and other with dual core ( 1 GHz). The dual core version comes with additional features including Dual Gigabit Ethernet, PCI Ex etc. There is no quad core in i.MX7.

Processors

The MX6 was based upon the Cortex A9 while the MX7 utilize the one or two Cortex A7 core paired with Cortex M4 MCU. The Cortex M4 is used to save power consumption by turning the A7 cores off substantially saving the power consumption and battery life. The Single core version of the i.MX7 will have 800 MHz Cortex A7 while the dual core one will have peak clock frequency of 1 GHz.

Power Efficiency

The main advantage of the MX7 is the power efficiency – its development is driven by the new consumer market consisting of Internet of things, home controls, wearable battery devices etc. Freescale is able to achieve lower power consumption by making the processor in a new “Low Power State Retention (LPSR) mode” that is said to consume only 250 μW. .

Evaluation Boards

One of the key reasons for using freescale ( and also the TI Line of processors) is their support in terms of documentation and the evaluation boards. Freescale’s newer i.MX7 is no exception. We see at least two evaluation boards for MX7 – one is the Sabre evaluation board, similar to that of the Sabre lite for i.MX6 which is expected to be a $500 evaluation board to be launched by freescale and other is an evaluation board by Arrow.

SABRE_LITE_for_mx7

The Arrow evaluation board is a smaller board ( measures 85x54x12 mm) compliant with the specification of the 96boards – we hope that it is a lower cost board with all the features. One key feature of this board is the integration of the Broadcom wifi and BLE chip into it.

Freescale_i.MX7_Arrow

Should you wait for i.MX8

If i.MX7 disappoints you with low processing power, you may like to look for i.MX8, that is slated to be launched later in 2015. It is expected to substantially more powerful than the i.MX6 using the more powerful 64 bit ARM processors – the Cortex A53 or the Cortex A57. We expect these to be at least twice as fast as the current quad core i.MX6. This should also have faster GPUs ( we do not know the details yet) and should support 4K resolution among other enhancements.

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