Spartan 6 Learner's board up and running

November 28th, 2015

Two months ago the Spartan 6 Learner's board PCB was released for prototype manufacturing. It was supposed to be released in October. But few things came up in between and after a delay of a month, the first prototype is up and running. And this is the subject of this post.


We are able to power up the board and are able to program it using Xilinx ISE tool. We started with a simple code that will take in the Switch SW3 and will display the LED2 when the switch is pressed. A simple verilog code is here

module LED_Button
input button_sw3,
output led2

assign led2 = ~button_sw3;


It also required the ucf file for the two pins used in the code

NET "led2" LOC = P131;
NET "button_sw3" LOC = P126;

Here is a video of board running the above code.

This code will verify both the Switches and both the LEDs

module LED_Buttom
input button_sw2, button_sw3,
output led1,led2

assign led1 = button_sw2; 
assign led2 = button_sw3;

The associated ucf file is

NET "led2" LOC = P131;
NET "button_sw3" LOC = P126;
NET "led1" LOC = P127;
NET "button_sw2" LOC = P124;

The board can be powered either by USB or by a Wall mount power supply that can take in wide range of input from 4.5V to 18V. The power supply from USB comes handy when you wish to debug your board while being connected with your laptop.

The board was built manually, obviously there was some scope of error. For example here is an example program that I tried to test the three seven segment display.

module LED_Buttom
input button_sw3,
output select_7seg3, sega,segb,segc,segd,sege,segf,segg,segdot

assign select_7seg3 = button_sw3;
assign sega = button_sw3;
assign segb = button_sw3;
assign segc = button_sw3;
assign segd = button_sw3;
assign sege = button_sw3;
assign segf = button_sw3;
assign segg = button_sw3;
assign segdot = button_sw3;

With the following section of ucf file


NET "button_sw3" LOC = P126;
NET "sega" LOC = P5;
NET "segb" LOC = P141;
NET "segc" LOC = P16;
NET "segd" LOC = P21;
NET "sege" LOC = P22;
NET "segf" LOC = P2;
NET "segg" LOC = P15;
NET "segdot" LOC = P17;

//NET "select_7seg1" LOC = P12; 
//NET "select_7seg2" LOC = P144;
NET "select_7seg3" LOC = P142;

It did work, however, the segments c and d did not work as ( corresponding to resistors R10 and R12 in the schematics) you can see in the picture below ( likely a manual assembly error).


The DIP switches were verified by making each segment of the 7 segment LED turn on and off based upon which switch is turned on or off. The following is the section of the ucf file for the 8 pins of the DIP switch.

NET "dip1" LOC = P23;
NET "dip2" LOC = P24;
NET "dip3" LOC = P26;
NET "dip4" LOC = P27;
NET "dip5" LOC = P29;
NET "dip6" LOC = P30;
NET "dip7" LOC = P32;
NET "dip8" LOC = P33;

The following code will test the 50 MHz oscillator on the board by blinking and LED.

module clk_div (

input clk,
output  led2    

    reg [32:0] counter;
    reg state;
    assign led2 = state;
    always @ (posedge clk)
        counter <= counter + 1;
        state <= counter[26]; // Changes when MSB changes


Of course you will need to assign 50 MHz clock input to Pin 55 as in the following ucf file.

NET "LED2" LOC = P131; //LED2
NET "clk" LOC = P55; // clk

The video of the LED blinking example

Update 11/29/2015

After touching up the 7 Segment area on the board, it was confirmed that the assembly was the issue.


The leaves us with the following things still to be verified

1. Booting from the Flash
2. UART Port communication using USB connector
5. SPI Bus A/D Converter


Minimal Hardware Configuration for XC6SLX9-2TQG144C

November 27th, 2015

When you are bringing up a new processor or FPGA board for the first time, you want to know the minimum set of hardware required to make the board boot. In the post I will go through the minimal set of components required to boot the Xilinx's popular XC6SLX9-2TQG144C , the 144 Pin Spartan 6 FPGA.

If you are releasing your new design you need to double and triple check these pins. A single mistake and it will be hard for you to proceed any further.

1. Power and Ground

The Xilinx XC6SLX9-2TQG144C requires three power supplies

VCCINT - This is the Power-supply for its internal core. The Pin numbers are 19,28,52,89,128. The typical power suppy is 1.2V. And yes, do not forget at least 4 decoupling capacitors ( 1 on Pins 19,28, one each on 52, 89 and 128).

VCCO - These are power supply pins for Output driver. Each of the 4 banks can have there own VCCO. In a typical design, these will all be at 3.3, assuming you are using 3.3V for output supplies. Each bank has 2 to 3 pins. Each of the 4 banks are along the 4 sides of the TFFP package. Again, it will be good to have 2 to 3 decoupling caps along on each of the 4 banks.

VCCAUX - Power supply pins for Auxilliary Circuits are typically at 3.3V

The figure below shows the section of the circuit with power supply.


2. Configuration Pins

Once you have the power supplies done correctly, you need to ensure that the configuration pins are done correctly. This circuit shows part of the schematics for configuration.


CMPCS_B_2 - - This pin ( Pin # 72) is reserved for Xilinx and is recommended to be left unconnected or connect High ( to VCCO). The best thing to do about this pin is to leave it unconnected. If you connect it to ground, you will see unexpected results.

SUSPEND - - This pin ( Pin # 73) - This is an Active high pin, to make the SPARTAN 6 go in power saving suspend mode. If you are not using this feature, connect this pin to ground.

PROGRAM_B_2 - Active-Low reset to configuration logic ( Pin #37). If for example, you are using an external SPI memory to load configuration, then making this pin low will reload the configuration. In the schematics below, this pin has been pulled high with a 0.1uF Cap for giving it a little time after power on to go high. A switch allows manual reloading of configuration. Do not press this switch when you are debugging with JTAG - you will have to reload the JTAG program.

Configuration Pins M1 and M2 - The Configuration Pins M1 ( Pin # 60) and M0 ( Pin #69) determines which and how the device will boot. When you are downloading your software using JTAG, these pins are dont care. In a typical configuration when you connect a 4 bit wide SPI Flash to boot the board, M1 will be 0 and M0 will be 1. The table shows other possible configuration ( the table is taken from Xilinx Datasheet).


Once you have done your power supplies correct and your configuration pins are done right you want to make sure that the JTAG Pins are connected properly. These Pins are TMS, TCK, TDO and TDI ( and of course the 3.3V and GND to the JTAG emulator). If these are done correctly, you should now be able to connect a JTAG programmer and be able to communicate with your SPARTAN 6.

Booting Standalone with SPI EEPROM

While the pins listed above will allow a JTAG to connect to your board, it will not be able to boot on its own. You will need to hook a SPI Flash ( and of course, program it with configuration bits) to be able to do that. The circuit shows the minimal configuration for the same.


Also make sure that you have a Clock on its Clock input Pin ( Pin # 55).


This post was prompted by the design of Spartan 6 Evaluation board for learning Verilog . The board is in my hand and is undergoing bring up and testing. Pin 90 ( that was supposed to be connected to VCCAUX) was connected to VCCINT, and that created board bring up issue. Stay tuned for more details.

Vikas Shukla


Building and copying Linux Kernel for i.MX6

November 11th, 2015

Recently I had to build the Kernel for i.MX6. The reason for this had to do with the integration of the TI-WI BLE ( a Wifi and Bluetooth Module) with the i.MX6.

The process of compiling was basically same as the compiling the uboot . But instead of giving command line


I added them in the Makefile

To compile - just give the make command


It takes some time so be patient. The output uImage is in the directory arch/arm/boot/.

Copying file to SD Card

It took some time to figure out how to copy the uImage to replace the existing uImage in SD Card. Basically, when you insert the SD Card in ubuntu it showed several pop up folders for different partitions in ubuntu. One of these was boot folder that had the uImage. Right clicking that folder -> Properties -> Basic shows the mount name as /media/vikas/root.


Once we know that we can copy the uImage with the following command

sudo cp arch/arm/boot/uImage /media/vikas/root/

This should get started if you are making change in kernel and then you wish to check out.


Removing unused internal pads from PCB Via

November 3rd, 2015

If you are using a via on a high speed net, chances are - it has excessive capacitance. The main source of the excess capacitance is the coupling between the via pads and the nearby power plane.

One quick way to reduce the via capacitance is to reduce the size of the pad. You start with the minimum drill size, which is typically 8 mils for most inexpensive PCB Fabrication processes. Now you need a minimum 4 mil trace for common inexpensive process which sets the minimum Via diameter size as 16 mils.


Even with the reduced pad size, the via is capacitive. The next step to reduce the capacitance is to increase the Antipad size. If you do not specify the antipad size, the separation between the via and the power plane is determined by the design rule of clearance between power plane flood and the nearest trace. For example if this clearance is set to be 4 mils, the diameter of the antipad can be assumed to be 24 mils or 8 mils more than the pad diameter of 16 mils. Typically if the antipad diameter is set to be 12 mils more than the pad size, we get reduced capacitance from via.

One final important way of reducing the via capacitance is the by removing the internal unused pads from via. These unused pads are more popularly called non functional pads. In a typical design, the pads are almost always present in the top and the bottom layers. Simplified via design has pads connected to all internal layers. So if a trace is going from top layer to bottom layer, the internal via pads are present even if not used. These internal unused pads add to the via capacitance. If you care for high speed designs, it is a good idea to consider removing these internal pads from the via. The separation between the via barrel and the power and ground plane increases, reducing the via capacitance.

You may extend the same concept by defining a new via from top layer to an internal layer. For example if you have an 8 layer board and you you are jumping from layer 1 to layer 6, you may remove via pad from all layers, except from 1( top) , 6 and 8 ( bottom). Each internal signal layer will require separate via definition(s).

Manufacturing Considerations

I am not a manufacturing expert, but there is one aspect that is certain - removing the Non Functional pads, does reduce the separation between the pads and the power plane and thereby reduces the chance of short, especially in the dense BGA areas. The PCB house, therefore, like to remove the Non Functional pads and potentially improve the yield.

There have been other discussion about the via barrel cracking and there are discussion about how the additional pads help keeping the barrel together. It appears that removal of the non functional pads does not create any disadvantage from manufacturing, yield or long term reliability perspective.

Via Back Drill

The removal of the Non Functional pad works at the design level ( or the gerber level). Another way to reduce the additional Capacitance is back drilling the pads. If a trace is going from Layer 1 to Layer 3 in a 8 Layer PCB, we have an extra stub from Layer 3 to Layer 8. Even if we remove the internal non functional pads, we have pads on layer 8. Back drilling is the process to remove the extra stub and the pad. This serves dual purpose - removal of the pad and the removal of the extra stub.

How about Non Functional Pads on Via for Power connections

Power connections are a totally different from high speed. In via for power plane, we wish to keep the length of the via drill to the minimum and we wish to keep capacitive coupling ( between power and ground ) high. The pad size in power via should be kept large to provide more capacitance. There is little discussion about the design of the via for delivering power nets. The design of via for the power nets will be guided by two basic principles - reducing the via drill inductance and more capacitive coupling between power and ground nets.

We expect your comments on this serious discussion.

By Vikas Shukla


PCB Via for High Speed Design

October 27th, 2015

The topic of PCB via and its capacitance with reference to the High Speed design was briefly discussed in the book Signal Integrity for PCB Designers, here . The topic requires a little more in depth analysis in 1 GHz and beyond range. Here are key points about via

1. The Via is predominantly capacitive. The top and the bottom pads of the via are main sources of the capacitance. Also the inner pads are electrically coupled with ground and power planes give additional capacitance. We should therefore try to minimize the size of the pad. It will require keeping the drill size to bare minimum. In most PCBs, the minimum drill size is of the order of 8 mils. Since the typical minimum trace width is 4 mils, the diameter of the pad is typically 16 mils at the minimum.

2. Enlarging the size of the antipad reduce the coupling of the pad and the drill with the ground layer and reduces the capacitance. For exact size of the antipad, a 3D simulation software should be used.

3. The drill length connecting the top and the bottom pad is predominantly inductive. This creates the inductive discontinuity. The length of this inductive discontinuity is typically 0.063 inch, which corresponds to 10.7 ps, assuming the speed of propagation in inner layer to be 170 ps per inch.

4. The inductive discontinuity starts playing role, when the rise time of the signal is less than 10x the electrical drill length of via. This rise time corresponds approximately to 107 ps. Whenever, time the rise time is less than about 100 ps, start considering the inductive discontinuity due to via. The lower the rise time, the more marked is the inductive discontinuity.

5. As a first order approximation, the via can be modeled as a pi circuit with two capacitor and one inductor as shown in following circuit.


The two capacitors correspond to the top and the bottom pads and the inductor correspond to the drill from top to the bottom.

6. As a first order the capacitance of the via can be given by the following formula.



εr = relative dielectric constant,
D1 = diameter of the via pad in inch,
D2 = diameter of the anti-pad in inch,
T = thickness of the PCB in inch,

7. According to the formula, increasing the Antipad size D2, and reducing the via diameter D1 reduces the via capacitance.

8. You can use the via capacitance calculator for a first order via capacitance calculator.

9. The above formula assumes that the inner ground layers are continuous and forms kind of a coaxial surface around the via drill. In that sense, it over estimates the via capacitance. In other words, it assumes presence of infinite number of ground planes. It also overestimates the effect if the anti pad. The formula also assumes that the size of the pads are same in the outer as well as the inner layers.

10. As a gross approximation, the via inductance can be estimated as


d = diameter of the drill hole in inch
h = thickness of the PCB ( or via length) in inch

11. The via inductance does not take into account any return path for the current. If there is a nearby via, the inductance of the loop will be substantially smaller.


Winter Sale of Signal Integrity for PCB Designer

October 12th, 2015

Signal Integrity for PCB Designers is now available for only $40 ( The price at amazon is $55).


Signal Integrity for PCB Designers 1st Ed by Vikas Shukla ISBN-13 978-0982136904